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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Mar 27, 2024 at 1:25=E2=80=AFPM Conor Dooley wro= te: > > From: Jamie Gibbons > > The GPIO controllers on PolarFire SoC were based on the "soft" IP > CoreGPIO, but the inp/outp registers are at different offsets. Add > compatible to allow for support of both sets of offsets. The soft > core will not always have interrupts wired up, so only enforce them for > the "hard" core on PolarFire SoC. > > Signed-off-by: Jamie Gibbons > Signed-off-by: Conor Dooley > --- Applied, thanks! Bart