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From: Andrew Halaney <ahalaney@redhat.com>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	"James E.J. Bottomley" <jejb@linux.ibm.com>,
	"Martin K. Petersen" <martin.petersen@oracle.com>,
	Hannes Reinecke <hare@suse.de>,
	Janek Kotas <jank@cadence.com>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	Avri Altman <avri.altman@wdc.com>,
	Bart Van Assche <bvanassche@acm.org>,
	Can Guo <quic_cang@quicinc.com>,
	Anjana Hari <quic_ahari@quicinc.com>
Cc: Andrew Halaney <ahalaney@redhat.com>,
	Will Deacon <will@kernel.org>,
	linux-arm-msm@vger.kernel.org,
	linux-scsi@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v5 01/11] scsi: ufs: qcom: Perform read back after writing
 reset bit
Date: Fri, 29 Mar 2024 15:46:43 -0500
Message-ID: <20240329-ufs-reset-ensure-effect-before-delay-v5-1-181252004586@redhat.com>
In-Reply-To: <20240329-ufs-reset-ensure-effect-before-delay-v5-0-181252004586@redhat.com>
References: <20240329-ufs-reset-ensure-effect-before-delay-v5-0-181252004586@redhat.com>
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Currently, the reset bit for the UFS provided reset controller (used by=0D
its phy) is written to, and then a mb() happens to try and ensure that=0D
hit the device. Immediately afterwards a usleep_range() occurs.=0D
=0D
mb() ensure that the write completes, but completion doesn't mean that=0D
it isn't stored in a buffer somewhere. The recommendation for=0D
ensuring this bit has taken effect on the device is to perform a read=0D
back to force it to make it all the way to the device. This is=0D
documented in device-io.rst and a talk by Will Deacon on this can=0D
be seen over here:=0D
=0D
    https://youtu.be/i6DayghhA8Q?si=3DMiyxB5cKJXSaoc01&t=3D1678=0D
=0D
Let's do that to ensure the bit hits the device. By doing so and=0D
guaranteeing the ordering against the immediately following=0D
usleep_range(), the mb() can safely be removed.=0D
=0D
Fixes: 81c0fc51b7a7 ("ufs-qcom: add support for Qualcomm Technologies Inc p=
latforms")=0D
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>=0D
Reviewed-by: Can Guo <quic_cang@quicinc.com>=0D
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>=0D
---=0D
 drivers/ufs/host/ufs-qcom.h | 12 ++++++------=0D
 1 file changed, 6 insertions(+), 6 deletions(-)=0D
=0D
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h=0D
index 9dd9a391ebb7..b9de170983c9 100644=0D
--- a/drivers/ufs/host/ufs-qcom.h=0D
+++ b/drivers/ufs/host/ufs-qcom.h=0D
@@ -151,10 +151,10 @@ static inline void ufs_qcom_assert_reset(struct ufs_h=
ba *hba)=0D
 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);=0D
 =0D
 	/*=0D
-	 * Make sure assertion of ufs phy reset is written to=0D
-	 * register before returning=0D
+	 * Dummy read to ensure the write takes effect before doing any sort=0D
+	 * of delay=0D
 	 */=0D
-	mb();=0D
+	ufshcd_readl(hba, REG_UFS_CFG1);=0D
 }=0D
 =0D
 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)=0D
@@ -162,10 +162,10 @@ static inline void ufs_qcom_deassert_reset(struct ufs=
_hba *hba)=0D
 	ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);=0D
 =0D
 	/*=0D
-	 * Make sure de-assertion of ufs phy reset is written to=0D
-	 * register before returning=0D
+	 * Dummy read to ensure the write takes effect before doing any sort=0D
+	 * of delay=0D
 	 */=0D
-	mb();=0D
+	ufshcd_readl(hba, REG_UFS_CFG1);=0D
 }=0D
 =0D
 /* Host controller hardware version: major.minor.step */=0D
=0D
-- =0D
2.44.0=0D
=0D