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Sat, 30 Mar 2024 09:30:35 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sat, 30 Mar 2024 02:30:31 -0700 Date: Sat, 30 Mar 2024 15:00:27 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski CC: Stephen Boyd , , , , , , , , , , , , , , Subject: Re: [PATCH v5 4/5] clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks Message-ID: References: <20240328075936.223461-1-quic_varada@quicinc.com> <20240328075936.223461-5-quic_varada@quicinc.com> <95f4e99a60cc97770fc3cee850b62faf.sboyd@kernel.org> <031d0a35-b192-4161-beef-97b89d5d1da6@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <031d0a35-b192-4161-beef-97b89d5d1da6@linaro.org> X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MCE8G2q1LBiie2LNQErgRJhK3oRwQD5V X-Proofpoint-GUID: MCE8G2q1LBiie2LNQErgRJhK3oRwQD5V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-30_05,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=750 clxscore=1015 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403300077 On Fri, Mar 29, 2024 at 01:10:03PM +0100, Krzysztof Kozlowski wrote: > On 29/03/2024 11:55, Varadarajan Narayanan wrote: > >>> + > >>> +enum { > >>> + ICC_ANOC_PCIE0, > >>> + ICC_SNOC_PCIE0, > >>> + ICC_ANOC_PCIE1, > >>> + ICC_SNOC_PCIE1, > >>> + ICC_ANOC_PCIE2, > >>> + ICC_SNOC_PCIE2, > >>> + ICC_ANOC_PCIE3, > >>> + ICC_SNOC_PCIE3, > >>> + ICC_SNOC_USB, > >>> + ICC_ANOC_USB_AXI, > >>> + ICC_NSSNOC_NSSCC, > >>> + ICC_NSSNOC_SNOC_0, > >>> + ICC_NSSNOC_SNOC_1, > >>> + ICC_NSSNOC_PCNOC_1, > >>> + ICC_NSSNOC_QOSGEN_REF, > >>> + ICC_NSSNOC_TIMEOUT_REF, > >>> + ICC_NSSNOC_XO_DCD, > >>> + ICC_NSSNOC_ATB, > >>> + ICC_MEM_NOC_NSSNOC, > >>> + ICC_NSSNOC_MEMNOC, > >>> + ICC_NSSNOC_MEM_NOC_1, > >>> +}; > >> > >> Are these supposed to be in a dt-binding header? > > > > Since these don't directly relate to the ids in the dt-bindings > > not sure if they will be permitted there. Will move and post a > > new version and get feedback. > > You can answer this by yourself by looking at your DTS. Do you use them > as well in the DTS? I can use them in the DTS. The icc-clk framework automatically creates master and slave nodes as 'n' and 'n+1'. Hence I can have something like this in the dt-bindings include file #define ICC_ANOC_PCIE0 0 #define ICC_SNOC_PCIE0 1 . . . #define ICC_NSSNOC_MEM_NOC_1 20 #define MASTER(x) ((ICC_ ## x) * 2) #define SLAVE(x) (MASTER(x) + 1) > It's a pity we see here only parts of DTS, instead of full interconnect > usage. Unfortunately cannot include the pcie dts changes with this patch, but you can refer to them at https://lore.kernel.org/linux-arm-msm/20230519090219.15925-5-quic_devipriy@quicinc.com/ The above macros will be used in the pcie node as follows pcie0: pci@28000000 { compatible = "qcom,pcie-ipq9574"; . . . interconnects = <&gcc MASTER(ANOC_PCIE0) &gcc SLAVE(ANOC_PCIE0)>, <&gcc MASTER(SNOC_PCIE0) &gcc SLAVE(SNOC_PCIE0)>; interconnect-names = "pcie-mem", "cpu-pcie"; . . . }; Hope this is acceptable. Thanks Varada