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AJvYcCVQrDiOhodEQ9BxKMAX4oxM9kM/hWlL9fG/Q3hFLYviiOcWj2+BZP/elFTyhBqfZY8xDOhjkeVEBVTe1myvkNNxNqLAwIydQFtohLmd X-Gm-Message-State: AOJu0YyTVUQ++97OCKol93fkLIfmPT46QvTji/yeK70b5lhafldtsKNQ fZ/NmVQl3mRekyAH9iBgnJMf1uPqHADFC83zwgE7vZ4pocG3OMi335xvHPyafB913Tj3+fptVCx AbZzhuavuYTovLim2xxipiPu/13WTVONmlgjEMQ== X-Received: by 2002:a5b:6cb:0:b0:dcc:57ff:fb70 with SMTP id r11-20020a5b06cb000000b00dcc57fffb70mr5248782ybq.60.1711849178283; Sat, 30 Mar 2024 18:39:38 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240330182817.3272224-1-quic_ajipan@quicinc.com> <20240330182817.3272224-8-quic_ajipan@quicinc.com> In-Reply-To: <20240330182817.3272224-8-quic_ajipan@quicinc.com> From: Dmitry Baryshkov Date: Sun, 31 Mar 2024 04:39:27 +0300 Message-ID: Subject: Re: [PATCH 7/7] clk: qcom: Add GPUCC driver support for SM4450 To: Ajit Pandey Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli Content-Type: text/plain; charset="UTF-8" On Sat, 30 Mar 2024 at 20:30, Ajit Pandey wrote: > > Add Graphics Clock Controller (GPUCC) support for SM4450 platform. > > Signed-off-by: Ajit Pandey > --- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gpucc-sm4450.c | 806 ++++++++++++++++++++++++++++++++ > 3 files changed, 816 insertions(+) > create mode 100644 drivers/clk/qcom/gpucc-sm4450.c > [skipped] > +static int gpu_cc_sm4450_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + > + regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > + > + /* Keep some clocks always enabled */ > + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ > + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ > + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ Why? At least other drivers model these three clocks properly. > + > + return qcom_cc_really_probe(pdev, &gpu_cc_sm4450_desc, regmap); > +} > + > +static struct platform_driver gpu_cc_sm4450_driver = { > + .probe = gpu_cc_sm4450_probe, > + .driver = { > + .name = "gpucc-sm4450", > + .of_match_table = gpu_cc_sm4450_match_table, > + }, > +}; > + > +module_platform_driver(gpu_cc_sm4450_driver); > + > +MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver"); > +MODULE_LICENSE("GPL"); > -- > 2.25.1 > > -- With best wishes Dmitry