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Date: Tue, 2 Apr 2024 01:07:58 +0100
From: Al Viro <viro@zeniv.linux.org.uk>
To: "Paul E. McKenney" <paulmck@kernel.org>
Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com,
	"David S. Miller" <davem@davemloft.net>,
	Andreas Larsson <andreas@gaisler.com>,
	Palmer Dabbelt <palmer@rivosinc.com>, Arnd Bergmann <arnd@arndb.de>,
	Marco Elver <elver@google.com>
Subject: Re: [PATCH RFC cmpxchg 2/8] sparc: Emulate one-byte and two-byte
 cmpxchg
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 <20240401223803.GZ538574@ZenIV>
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On Mon, Apr 01, 2024 at 04:58:03PM -0700, Paul E. McKenney wrote:
> > #define CMPXCHG(T)	\
> > 	T __cmpxchg_##T(volatile ##T *ptr, ##T old, ##T new)	\
				 ^^^

*blink*

I understand what search-and-replace has produced that, but not
how I hadn't noticed the results...  Sorry ;-/

> > 	{							\
> > 		unsigned long flags;				\
> > 		##T prev;					\
> > 								\
> > 		spin_lock_irqsave(ATOMIC_HASH(ptr), flags);	\
> > 		if ((prev = *ptr) == old)			\
> > 			*ptr = new;				\
> > 		spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags);\
> > 		return prev;					\
> > 	}
> > 
> > CMPXCHG(u8)
> > CMPXCHG(u16)
> > CMPXCHG(u32)
> > CMPXCHG(u64)
> > 
> > in arch/sparc/lib/atomic32.c, replacing equivalent __cmpxchg_u{32,64}()
> > definitions already there and use of those in that switch in __cmpxchg()
> > definition...
> 
> Fair enough, and ATOMIC_HASH() is set up to permit mixed-size atomic
> accesses courtesy of ignoring the bottom bits, though ignoring more
> of them than absolutely necessary.  Maybe 32-bit sparc has 32-byte
> cache lines?

It does, IIRC.

> Would you like to do that patch?  If so, I would be happy to drop mine
> in favor of yours.  If not, could I please have your Signed-off-by so
> I can do the Co-developed-by dance?

Will do once I dig my way from under the pile of mail (sick for a week
and subscribed to l-k, among other lists)...