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Date: Tue, 2 Apr 2024 12:09:59 +0100
From: Sudeep Holla <sudeep.holla@arm.com>
To: Sibi Sankar <quic_sibis@quicinc.com>
Cc: <cristian.marussi@arm.com>, <andersson@kernel.org>,
	<konrad.dybcio@linaro.org>, <jassisinghbrar@gmail.com>,
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	<devicetree@vger.kernel.org>, <quic_rgottimu@quicinc.com>,
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	Ulf Hansson <ulf.hansson@linaro.org>, <quic_psodagud@quicinc.com>
Subject: Re: [PATCH 5/5] arm64: dts: qcom: x1e80100: Enable cpufreq
Message-ID: <Zgvnh0J2a_fBH0bR@bogus>
References: <20240328095044.2926125-1-quic_sibis@quicinc.com>
 <20240328095044.2926125-6-quic_sibis@quicinc.com>
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On Thu, Mar 28, 2024 at 03:20:44PM +0530, Sibi Sankar wrote:
> Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node.
> 
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 4e0ec859ed61..d1d232cd1f25 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -68,6 +68,7 @@ CPU0: cpu@0 {
>  			compatible = "qcom,oryon";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
>  			next-level-cache = <&L2_0>;
>  			power-domains = <&CPU_PD0>;
>  			power-domain-names = "psci";


Any reason why you wouldn't want to use the new genpd based perf controls.
IIRC it was added based on mainly Qcom platform requirements.

-                     clocks = <&scmi_dvfs 0>;
		      next-level-cache = <&L2_0>;
-  		      power-domains = <&CPU_PD0>;
-  		      power-domain-names = "psci";
+                     power-domains = <&CPU_PD0>, <&scmi_dvfs 0>;
+                     power-domain-names = "psci", "perf";


And the associated changes in the scmi dvfs node for cells property.

This change is OK but just wanted to check the reasoning for the choice.

--
Regards,
Sudeep