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From: Frank Li <Frank.Li@nxp.com>
Date: Tue, 02 Apr 2024 10:33:47 -0400
Subject: [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support
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To: Richard Zhu <hongxing.zhu@nxp.com>, 
 Lucas Stach <l.stach@pengutronix.de>, 
 Lorenzo Pieralisi <lpieralisi@kernel.org>, 
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 Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, 
 Pengutronix Kernel Team <kernel@pengutronix.de>, 
 Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, 
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 Mark Brown <broonie@kernel.org>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>
Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, 
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
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 =?utf-8?B?eUx2NWJ1cDI1UzFncHNWUUdPeU1qazVjN0FLSDRtSTdvZFdXam5ESmRXU0Rs?=
 =?utf-8?B?R1laTitOc21TdEpld2l3RjFXRW1KWFhycktuNWJ3QWQzRlUxL2haYWlkazM0?=
 =?utf-8?B?M21RL0xrQU9hc25hZnY4dHk4TGVMV3hza0J6U3NybGJUeDVqN3BWbjVSdHp0?=
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 =?utf-8?B?SERLR1FvT0VoNXo4aFlLd00xS3Rid2s4WUNUd210NDJ4b1BFTjZMM1NYS2VW?=
 =?utf-8?B?SFExdUg2UU9MR084a1NSMXVTTnRXbjRWcWdmWWJ2bm5sRlEyRFBZVjk1VnJl?=
 =?utf-8?B?a000MGFjYnFvTzhmbjhoVVA2UThoS1NmaHg3WFZEbVFHRml5c1pVa3Y4elhR?=
 =?utf-8?B?Q0FrR1NhaGR3M1pjTlZyanhJbHBWYTk2em9xNjUweXBQTVdyaUQ5OVJqWmtZ?=
 =?utf-8?B?VXlMem1FQ0VQcDlDMWduQ21wWklXelp6cEkyeHhUQ0tyRkJtQ0hsVTZodHll?=
 =?utf-8?B?OUQ0SGgzbzdBckE4NVN5akRmTHQ3TFo0YnU0ZDducGoyVnZCVncwSFlFcC93?=
 =?utf-8?B?NHFCRXlwTy9mOGtBQmFpNlVIYjdGb2dLaURyU1diZkdEUjdPai9VbEdYSlUy?=
 =?utf-8?B?TUNZS3pneDJ3WDJEZHFnNHF5WGY4TjlKaTBQMGNaVnNwbXp0dEg1MFgwa0w5?=
 =?utf-8?B?aVEza2l0Sklld0NJQWRsVmV6b3VmbFB0dWlnejlBNnVoaVk5OHlPZEgvSDla?=
 =?utf-8?B?V2pxOEFvbFVFbk00UWE0bGhFcW9ndlF1VWZKNUJuR3ZYK2lkVFBZZU5EK25G?=
 =?utf-8?B?VmdzWUo2RWpMYXJRaTN2a01hdlpsYklVRzFBZXdIRFpyN3ExK1ZqUEs5a3Ra?=
 =?utf-8?B?WFJGRGlZTU5iT00rN1VlR2pjUmpmRUQ0RzdqN2IxM0VTUnVGc3BHVTFXMzZt?=
 =?utf-8?B?RmUrMTFrT3VBZ1BmQlhUWS9xbFJoRmFmZGZoMFRBRVVDWHlrbzdqQ3pMSGJa?=
 =?utf-8?B?UTd5ZDBNbVZKUnllVGN3R2lBbFdlay94QWU0RGlGMWM4VkswSFVoK1RuK2Zm?=
 =?utf-8?B?Q2hwY3FSSEEwTmRMRnNuVmhnMXlFMDA0cXptOWVhSkN0OWFnMEdyWlk3U1ZI?=
 =?utf-8?B?cXQ5NmtYcW1DWkF2dG9OT05RZEtEOE8xZm9rK3ozSUc4RUpKOFBrNWpTMlZz?=
 =?utf-8?B?bm54a05qV2Z4TU5jeGkvN2lEMEdidWM1RmF0UkprU3F6UjBUazRhOWNuOGRo?=
 =?utf-8?B?NUgxd3RPNHkzSjBXZGQ0aHVIOEdCSlB3Vlg1TmtUREY0TVJ6OHVEWFlveXdG?=
 =?utf-8?B?elYvWjNJT0g3Y1FPcXM0UFlOUjhlNkI5U0RrMmoxQll3S21ROHFSSmhiTFI2?=
 =?utf-8?B?UVdKbFpLb21tcjNBUkJsR3hxaGRLaTZKaUJDaHVRTUNYVW92cWVrcVRyY3JP?=
 =?utf-8?B?Rldack9SeElNQlFJcnpyMWhBbjJGaVl1WFpJcGdEVkxmK0t4eGVuTHp6OHlv?=
 =?utf-8?B?ZHRyaWk2REloeVBNMGdiOFBLZ2k4WFBNUmtzSTFzTkU3emNhZk8wSDJHdFN2?=
 =?utf-8?B?aVBHdGJXaStwMUxCZ2NlN0lpZytNMGpSRmZsZ080eENyMjlxekxuS2VBUUN5?=
 =?utf-8?B?QW9Md1JFMmVkUkcyWWdGd3dkRENWUnpndk1wNlJBYy8yUndrRmRvVXFXa3p4?=
 =?utf-8?Q?d4IM=3D?=
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From: Richard Zhu <hongxing.zhu@nxp.com>

Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
index 378808262d16b..af7c79e869e70 100644
--- a/drivers/pci/controller/dwc/pcie-imx.c
+++ b/drivers/pci/controller/dwc/pcie-imx.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/reset.h>
 #include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
 
@@ -81,6 +82,7 @@ enum imx_pcie_variants {
 	IMX8MQ,
 	IMX8MM,
 	IMX8MP,
+	IMX8Q,
 	IMX95,
 	IMX8MQ_EP,
 	IMX8MM_EP,
@@ -96,6 +98,7 @@ enum imx_pcie_variants {
 #define IMX_PCIE_FLAG_HAS_PHY_RESET		BIT(5)
 #define IMX_PCIE_FLAG_HAS_SERDES		BIT(6)
 #define IMX_PCIE_FLAG_SUPPORT_64BIT		BIT(7)
+#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP		BIT(8)
 
 #define imx_check_flag(pci, val)     (pci->drvdata->flags & val)
 
@@ -132,6 +135,7 @@ struct imx_pcie {
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
+	u32			local_addr;
 	struct reset_control	*pciephy_reset;
 	struct reset_control	*apps_reset;
 	struct reset_control	*turnoff_reset;
@@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
 	if (!drvdata->mode_mask[id])
 		id = 0;
 
+	/* If mode_mask is 0, means use phy driver to set mode */
+	if (!drvdata->mode_mask[id])
+		return;
+
 	mask = drvdata->mode_mask[id];
 	val = mode << (ffs(mask) - 1);
 
@@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
 	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
 	const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
 
+	phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
 	if (drvdata->ltssm_mask)
 		regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
 				   drvdata->ltssm_mask);
@@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
 	struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
 	const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
 
+	phy_set_speed(imx_pcie->phy, 0);
 	if (drvdata->ltssm_mask)
 		regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
 				   drvdata->ltssm_mask, 0);
@@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_clk_disable;
 		}
 
+		ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+		if (ret) {
+			dev_err(dev, "unable to set pcie PHY mode\n");
+			goto err_phy_off;
+		}
+
 		ret = phy_power_on(imx_pcie->phy);
 		if (ret) {
 			dev_err(dev, "waiting for PHY ready timeout!\n");
@@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
 		regulator_disable(imx_pcie->vpcie);
 }
 
+static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
+{
+	struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
+	struct dw_pcie_ep *ep = &pcie->ep;
+	struct dw_pcie_rp *pp = &pcie->pp;
+	struct resource_entry *entry;
+	unsigned int offset;
+
+	if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
+		return cpu_addr;
+
+	if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
+		offset = ep->phys_base;
+	} else {
+		entry = resource_list_first_type(&pp->bridge->windows,
+						 IORESOURCE_MEM);
+		offset = entry->res->start;
+	}
+
+	return (cpu_addr + imx_pcie->local_addr - offset);
+}
+
 static const struct dw_pcie_host_ops imx_pcie_host_ops = {
 	.init = imx_pcie_host_init,
 	.deinit = imx_pcie_host_exit,
@@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
 static const struct dw_pcie_ops dw_pcie_ops = {
 	.start_link = imx_pcie_start_link,
 	.stop_link = imx_pcie_stop_link,
+	.cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
 };
 
 static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
@@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
 					     "Failed to get PCIEPHY reset control\n");
 	}
 
+	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
+		ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr);
+		if (ret)
+			return dev_err_probe(dev, ret, "Failed to get local-address");
+	}
+
 	switch (imx_pcie->drvdata->variant) {
 	case IMX8MQ:
 	case IMX8MQ_EP:
@@ -1605,6 +1650,7 @@ static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
 static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
 static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
 static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
+static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
 
 static const struct imx_pcie_drvdata drvdata[] = {
 	[IMX6Q] = {
@@ -1708,6 +1754,13 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 		.set_ref_clk = imx8mm_pcie_set_ref_clk,
 	},
+	[IMX8Q] = {
+		.variant = IMX8Q,
+		.flags = IMX_PCIE_FLAG_HAS_PHYDRV |
+			 IMX_PCIE_FLAG_CPU_ADDR_FIXUP,
+		.clk_names = imx8q_clks,
+		.clks_cnt = ARRAY_SIZE(imx8q_clks),
+	},
 	[IMX95] = {
 		.variant = IMX95,
 		.flags = IMX_PCIE_FLAG_HAS_SERDES,
@@ -1785,6 +1838,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
 	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
 	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
 	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
+	{ .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
 	{ .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
 	{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
 	{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },

-- 
2.34.1