Received-SPF: pass (google.com: domain of linux-kernel+bounces-128551-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Message-ID: <025ed42a-c6f2-48e6-a8d1-b6de79d6957b@nvidia.com>
Date: Tue, 2 Apr 2024 20:15:55 +0100
User-Agent: Mozilla Thunderbird
Subject: Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional
Content-Language: en-US
To: Sumit Gupta <sumitg@nvidia.com>, krzysztof.kozlowski@linaro.org,
 robh@kernel.org, conor+dt@kernel.org, maz@kernel.org, mark.rutland@arm.com,
 treding@nvidia.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-tegra@vger.kernel.org, amhetre@nvidia.com, bbasu@nvidia.com
References: <20240402132626.24693-1-sumitg@nvidia.com>
 <20240402132626.24693-2-sumitg@nvidia.com>
From: Jon Hunter <jonathanh@nvidia.com>
In-Reply-To: <20240402132626.24693-2-sumitg@nvidia.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?VmtuRHMwOVZteElFSkJlN2pBNTJUVlFQSHNsam1Wd24zdzhld2VmZFF1bHcz?=
 =?utf-8?B?OXNEWjZTUUp5TUV4WGhDMmYxdWZZNHdCZkJ5QjdnRGlqUGd0Y2VOU0VIb2du?=
 =?utf-8?B?M1JDMUxVL1JsVG1yaUFWdFNZSmhkMjE3UHlLcjdjSVZyYzFjTHVmOW1UV3R6?=
 =?utf-8?B?SmZ1bU94eTcwbFFNUHJzcDJwN1B5bExoNXBuckptd0Y0eStqTU5CbGhXVHFP?=
 =?utf-8?B?Vzdwdlh0eThMUHkwZkdsdmhSYTM0b1l1NGxxVjFkdkN3NmlHLzlsVlVmTit1?=
 =?utf-8?B?WlozcVA1VWZUTVdvMFV0S3Zxb1E0V3lNWmJhem5yUExDaVltVkVCNVhab1A3?=
 =?utf-8?B?bldhdkpySUZ2dDZCNVJ6SUV0UFd3QTFENmNzby81elhCTWtiQjZMeW9hUFFY?=
 =?utf-8?B?R2FDdWltVXlGS2FpR0hSTG00cWtMVXRFenErNG0xRnJUVFJXbFVlMzVWeWVa?=
 =?utf-8?B?U21wTmttZnFnSEt6TTF1VXJGSkF0bE1Tdi9oeXR2SWtIakR2clphaHFGSzRS?=
 =?utf-8?B?aStvVEdZK1huMWJ6Q1g2T3F3MHZKd1B3bE04RFhBbVNoSm0vcFNnWE9OUWNP?=
 =?utf-8?B?VzRwR1l1bnJqUTB3Nk9aRnRQeTJraE95Q0RiOG5IMU5ZKzExK2JUWUd1L1ZL?=
 =?utf-8?B?TTdBeWR6U0hNTVRwczlFdkJTTG15ZzE3Umh3aEtHOGhOZjJ2cDAxeWhOa1hX?=
 =?utf-8?B?ZHBsRHVvVjJ0U2x0R0lVUHpFeG83Njk2SkN4VHJ3dW5WVjQ0aWNBaC9uRG1a?=
 =?utf-8?B?aFI4SmppbVNVeklnYkxuK3VhYW8wSmJvcmc2MW5KOTBScitKYU5kRG5CdDY1?=
 =?utf-8?B?cHVjT0pTRE9uV2VJWHFKM0tYL0sxanN3MEdEejN3RXVaL3d3R3VTck5IYTVN?=
 =?utf-8?B?UGxjLzUrV1NCUUE2OXgrcHBGSXZ1VzA1cUh4OVk0VUhvV0MxNUZScHNXUDRB?=
 =?utf-8?B?T2RmSjU2cnMxVzBHNHowd2M0TEZRdiswUnI0dUZhUUxKUTF3Q01xWDYwTVdn?=
 =?utf-8?B?cWRja0hpZ3ZRb0U1YWh2Z1V6U1M5QndIb0h0OHpQeFVnZE1TU1JZaFJNNHRO?=
 =?utf-8?B?Mm43b3dGcC9IRjlmdTRJb1BOTGRNaWZxSFlpV3h5cEh4a2dKRi9FSGczdjFK?=
 =?utf-8?B?RytudThUcXpsbDQyWWY5RTZXTm5kNFFFUWlZL3IzQVR3WjB5ZXlZNUdoL2tj?=
 =?utf-8?B?QkJXKzcxbFVCRXJ1YmJDbmJicW1Nd2d1M0gydHRrZWtZb2tDMlNGVldITHYy?=
 =?utf-8?B?SjBjUFVMbjZEQW9RcG5lam1qNDFZQWxjc2RpV1JwVkp2b0dYbFNFRnluQjZR?=
 =?utf-8?B?amVqOXNjMTB5dTl2M2JVWHBWd2FXUUhWVk1RWjIzdWdpUE5yczdLcklXTVN2?=
 =?utf-8?B?eW5ubUJLenNGWFFkNWlwaTByVGVsNytDSGZUYWJiNjVBeDY4dWJEV3VENzRT?=
 =?utf-8?B?UmFDenVGcElqK04yblA4T3o3MHVlOGRLY1lDbkxEcC81N0FwMmJSSUszRThu?=
 =?utf-8?B?cWZwSEhLanhRTEtlaWhuS0hmM2JrYUpJNzlWM1gySWs0WjY0M0E0d2ZEZEtE?=
 =?utf-8?B?aUZOeUIyR0JTT0ttMXBtalhoeEF0SnkwUzNTVVozNS8zR2J1K3UrbGtYa1RC?=
 =?utf-8?B?SmdjdVFOcGhDOVNZcVNkUWV5MlRib1pUaVZBK2xIQjR2WmFmanQ1YmoxbFYw?=
 =?utf-8?B?RjVNVFhUYWRwcFdHODZuTlkrZ1FjUkdON3grUThkcjF0ZHJLc1RtQnhTNHNR?=
 =?utf-8?B?a01zUEYzdmQwSm5iQy9Fa0lheThMTUdMYXIwL3FZM0oxOGpLQTA5c003S0tH?=
 =?utf-8?B?UlJtQVNjbUxNOE9IMFlnUXR2WTNkbXByVUdXQVg5V3hQUjhqVzJKVVZOZnpp?=
 =?utf-8?B?dkQ1NXdVaU5RUW01Wk01bEZYQkF2NmVMMDlhYXRjVlFtTkZxK1AwTU9XL1lK?=
 =?utf-8?B?VEhSTThWYlE4aUkyS1ZzRm5tbHl2WGVYMGNFWW1ZOTNoRkxxbjZmMExzSGxp?=
 =?utf-8?B?SkFXcFd1OGNNRzJERmMyRzR4UjN6UzZ2R3dUMVFBQlpDUTBxcXJNdVV3aVVO?=
 =?utf-8?B?L293U0NYek90SHNSdXRjd1h3RTFnRFhtWXF3MERtNENhQ2dlbGNoUHFlZ3NS?=
 =?utf-8?Q?7Vy0AaqxEWNn7xMaV8vI9s102?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: f6f73b5a-3e6b-47f3-65f9-08dc53495528
X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5444.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2024 19:16:01.3294
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: r7vNNLekO8QLpn4hdU9b892EOT5b6yQP7FkhzP+BRC9GzLNFda8ulWS4ezNK4CfjLsqNHpPgAw0QrxofGL+4sg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8752


On 02/04/2024 14:26, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
> Make both the regions as optional for SoC's from Tegra186 onwards.
> Tegra MC driver will skip access to the restricted registers from Guest
> if the respective regions are not present in the memory-controller node
> of Guest DT.
> 
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
>   .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> index 935d63d181d9..c52c259f7ec5 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> @@ -146,17 +146,17 @@ allOf:
>       then:
>         properties:
>           reg:
> -          maxItems: 6
> +          maxItems: 4

minItems?

Jon

-- 
nvpublic