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AJvYcCXVmQHOIHM26MQ+I9jkZutczUmo7W01Vi7yZE0LUyEDt+Py7sv0oCYcbWu/1yodaJOJ2MUFoOEaKmkWXM2CUS4tczjI57gAF+VBtdx1 X-Gm-Message-State: AOJu0YxzCPD/Mj6OCItKTUBijzvqVhyjZ8Mgwfb5+ZZqe8qMZkggbQGa uZDeH419ERaXv1FWAatcGcb2d40kQS+WZ0X49PZDQ64nWlH4PmLaXrE6SMKN3il0P+W7BNU0a6U JLvLSAsZPdJuDo4J3UDRYXDNvbDH9co8mctACXA== X-Received: by 2002:a25:741:0:b0:dd0:129f:16 with SMTP id 62-20020a250741000000b00dd0129f0016mr11007422ybh.11.1712085839219; Tue, 02 Apr 2024 12:23:59 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240330182817.3272224-1-quic_ajipan@quicinc.com> <20240330182817.3272224-8-quic_ajipan@quicinc.com> <9106b0eb-e15d-f2fa-d681-4017412c4a76@quicinc.com> In-Reply-To: <9106b0eb-e15d-f2fa-d681-4017412c4a76@quicinc.com> From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 22:23:48 +0300 Message-ID: Subject: Re: [PATCH 7/7] clk: qcom: Add GPUCC driver support for SM4450 To: Ajit Pandey Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli Content-Type: text/plain; charset="UTF-8" On Tue, 2 Apr 2024 at 21:26, Ajit Pandey wrote: > > > > On 3/31/2024 7:09 AM, Dmitry Baryshkov wrote: > > On Sat, 30 Mar 2024 at 20:30, Ajit Pandey wrote: > >> > >> Add Graphics Clock Controller (GPUCC) support for SM4450 platform. > >> > >> Signed-off-by: Ajit Pandey > >> --- > >> drivers/clk/qcom/Kconfig | 9 + > >> drivers/clk/qcom/Makefile | 1 + > >> drivers/clk/qcom/gpucc-sm4450.c | 806 ++++++++++++++++++++++++++++++++ > >> 3 files changed, 816 insertions(+) > >> create mode 100644 drivers/clk/qcom/gpucc-sm4450.c > >> > > > > [skipped] > > > >> +static int gpu_cc_sm4450_probe(struct platform_device *pdev) > >> +{ > >> + struct regmap *regmap; > >> + > >> + regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc); > >> + if (IS_ERR(regmap)) > >> + return PTR_ERR(regmap); > >> + > >> + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > >> + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > >> + > >> + /* Keep some clocks always enabled */ > >> + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ > >> + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ > >> + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ > > > > Why? At least other drivers model these three clocks properly. > > > These clocks are POR on in SM4450 and required to be kept always enabled > for GPU functionality hence keep them enabled from probe only. Please, check how this is handled on the other platforms, please. Hint: `git grep GPU_CC_DEMET_CLK` > > >> + > >> + return qcom_cc_really_probe(pdev, &gpu_cc_sm4450_desc, regmap); > >> +} > >> + > >> +static struct platform_driver gpu_cc_sm4450_driver = { > >> + .probe = gpu_cc_sm4450_probe, > >> + .driver = { > >> + .name = "gpucc-sm4450", > >> + .of_match_table = gpu_cc_sm4450_match_table, > >> + }, > >> +}; > >> + > >> +module_platform_driver(gpu_cc_sm4450_driver); > >> + > >> +MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver"); > >> +MODULE_LICENSE("GPL"); > >> -- > >> 2.25.1 > >> > >> > > > > > > -- > Thanks, and Regards > Ajit -- With best wishes Dmitry