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(unknown [10.252.69.73]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240403024240epsmtip19cb057068cd3e71f4860396bd34d82d1~CpPBO8iGd2042120421epsmtip1d; Wed, 3 Apr 2024 02:42:40 +0000 (GMT) From: Seongsu Park To: will@kernel.org, catalin.marinas@arm.com, ardb@kernel.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sgsu.park@samsung.com, Leem ChaeHoon , Gyeonggeon Choi , Soomin Cho , DaeRo Lee , kmasta Subject: [PATCH v2] arm64: Fix double TCR_T0SZ_OFFSET shift Date: Wed, 3 Apr 2024 11:42:36 +0900 Message-Id: <20240403024236.193428-1-sgsu.park@samsung.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIJsWRmVeSWpSXmKPExsWy7bCmga7CIZ40g1nPDCx+fnnPaPF+WQ+j xaa2+4wWfzbuZrL48ncps8Wmx9dYLS7vmsNmsfT6RSaL9w1drBaTfmxhtGj//ILVouWOqQOP x5p5axg9ds66y+6xaVUnm8fmJfUefVtWMXocOruA1ePzJrkA9qhsm4zUxJTUIoXUvOT8lMy8 dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygO5UUyhJzSoFCAYnFxUr6djZF+aUl qQoZ+cUltkqpBSk5BWYFesWJucWleel6eaklVoYGBkamQIUJ2Rmbnm5lL9jGXbHh8132BsYH nF2MHBwSAiYS/5eYdTFycQgJ7GCUuPX5FguE84lR4tGsZkY45/7UZUAZTrCOeXePMoPYQgI7 GSUOv/KGK1rcdwusiE1AS2L1v152EFtEIFTi2c77YGOZBWYxSSw4uhesSFjAWqL93Dwwm0VA VeLo9jVMIDfxAsWfnDOGWCYvsf/gWbBlvAKCEidnPgErZwaKN2+dzQwyU0LgL7tE375LUNe5 SKx8sJ8ZwhaWeHV8CzuELSXxsr8Nyi6W2PdlDVRNjcSDeXugbHuJjmdtLCA3MAtoSqzfpQ+x i0/i3dceVkhw8Up0tAlBmMoS57Y6QpiSEn8W6EHM8JBYcWsLIyR0YiU+n/nGMoFRbhaS+2ch uX8WwqoFjMyrGMVSC4pz01OTDQsM4bGYnJ+7iRGcNrWMdzBenv9P7xAjEwfjIUYJDmYlEd6f 3pxpQrwpiZVVqUX58UWlOanFhxhNgQE6kVlKNDkfmLjzSuINTSwNTMyMTCyMLY3NlMR5z1wp SxUSSE8sSc1OTS1ILYLpY+LglGpg4mXh2JtcoRhbMlWK/8mlK7ckd+9eLsyXpeHzmmG9+/WS E+EbK0WW1cb1rn8pV2gy+7DW95QKMc3K1ex3r214wy7PYDD77DlHH9u2vp3TFV+Hf+03Y05s 7z9tlfrejvmz4ZwljYcel5nl6e3Vq17wia3FKETD+fyLPyl9s8qqtAXPmevvmXd9yqOlPxv3 7pE54SzcWBH2W9Tyb3raqj6XpI2vi8XusduEShu93Nf/kWtK6MLmkP5m0aUTTux3+yBb2RH2 pkP+/IJ3gSXfgvaV3/60o9HEp+CklM/U46c/alx3iDPYt8w9wrPAmmfF72iZxZbFa/ZNDD26 fwOPX3ip41nP3zMOzYqW2uYRN+GtEktxRqKhFnNRcSIA0ddQSCQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWy7bCSnK7CIZ40g89bZC1+fnnPaPF+WQ+j xaa2+4wWfzbuZrL48ncps8Wmx9dYLS7vmsNmsfT6RSaL9w1drBaTfmxhtGj//ILVouWOqQOP x5p5axg9ds66y+6xaVUnm8fmJfUefVtWMXocOruA1ePzJrkA9igum5TUnMyy1CJ9uwSujE1P t7IXbOOu2PD5LnsD4wPOLkZODgkBE4l5d48ydzFycQgJbGeUePPyCzNEQlKi/d1lli5GDiBb WOLw4WKQsJDAB0aJ37sSQGw2AS2J1f962UFsEYFIibeXb7GCzGEWWMQk8WVtI9gcYQFrifZz 81hAbBYBVYmj29cwgczkBYo/OWcMsUpeYv/Bs2DlvAKCEidnPgErZwaKN2+dzTyBkW8WktQs JKkFjEyrGEVTC4pz03OTCwz1ihNzi0vz0vWS83M3MYKDWytoB+Oy9X/1DjEycTAeYpTgYFYS 4f3pzZkmxJuSWFmVWpQfX1Sak1p8iFGag0VJnFc5pzNFSCA9sSQ1OzW1ILUIJsvEwSnVwBSg Pvddp5OOy/fJH9yKavwrum7UZXALqhc8kNMre1If90c874X4X5GpBiyd1RPuTtbsqDq7ejNP 4MWOJda/GM7mxiy9fSp/KpN1Sq91+4d0/ofP0kI8T25+GNCcrO51WNSp1W3n5d8pMY22ok8i jLp3K70K6V/Oc2BfwvW7yxzPrnj04ufSwozrc76tVT5zZOvcPEVOU9nKIsO4E/8Lrd80L/JI /abJvCl083rnwvSsPzGq3/8UxFlvNwu7I7nN/siZ35Wds+0WLmGr8pztIC5rrBSp5L72J2Pj jZAL/2U/lNRu0s4+ullgl7nIfaeElBM/furPWaGaLSpwk+nlGceLOpKz/58o6j/2qGbvVyWW 4oxEQy3mouJEAFs8awrdAgAA X-CMS-MailID: 20240403024240epcas1p155cd55ca8c1dae6114b970cf3f57084e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240403024240epcas1p155cd55ca8c1dae6114b970cf3f57084e References: We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. So, the TCR_T0SZ_OFFSET shift here should be removed. Co-developed-by: Leem ChaeHoon Signed-off-by: Leem ChaeHoon Co-developed-by: Gyeonggeon Choi Signed-off-by: Gyeonggeon Choi Co-developed-by: Soomin Cho Signed-off-by: Soomin Cho Co-developed-by: DaeRo Lee Signed-off-by: DaeRo Lee Co-developed-by: kmasta Signed-off-by: kmasta Signed-off-by: Seongsu Park --- Changes in v2: - Condition is updated --- arch/arm64/include/asm/mmu_context.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index c768d16b81a4..bd19f4c758b7 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) { unsigned long tcr = read_sysreg(tcr_el1); - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) + if ((tcr & TCR_T0SZ_MASK) == t0sz) return; tcr &= ~TCR_T0SZ_MASK; - tcr |= t0sz << TCR_T0SZ_OFFSET; + tcr |= t0sz; write_sysreg(tcr, tcr_el1); isb(); } -- 2.34.1