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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN1PR18MB2126.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 96f6baa9-b1d9-4bf5-4e8f-08dc539e0aba X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2024 05:22:22.9061 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 47DZsTglweNXCqVAOJS0lAr/bwaG/fwJo+Pe+5AvfKB1A6RMnK8BrESq2PC2wUPS066fdfGt1eJVRsMnxO/5EfPKnAmQcJEnQm6cCkkU01Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3447 X-Proofpoint-GUID: JnKgLSNZpmmzp9_uAos9OAoyOXR3pGr8 X-Proofpoint-ORIG-GUID: JnKgLSNZpmmzp9_uAos9OAoyOXR3pGr8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_04,2024-04-01_01,2023-05-22_02 Hi Andrew, Please find the responses inline. Thanks, Gowthami > -----Original Message----- > From: Andrew Lunn > Sent: Wednesday, March 27, 2024 6:41 PM > To: Gowthami Thiagarajan > Cc: will@kernel.org; mark.rutland@arm.com; linux-arm-kernel@lists.infrade= ad.org; linux- > kernel@vger.kernel.org; Sunil Kovvuri Goutham ; Geo= rge Cherian > ; Linu Cherian > Subject: [EXTERNAL] Re: [RESEND PATCH v3] perf/marvell: Marvell PEM perfo= rmance monitor support >=20 > On Wed, Mar 27, 2024 at 12:51:17PM +0530, Gowthami Thiagarajan wrote: > > PCI Express Interface PMU includes various performance counters > > to monitor the data that is transmitted over the PCIe link. The > > counters track various inbound and outbound transactions which > > includes separate counters for posted/non-posted/completion TLPs. > > Also, inbound and outbound memory read requests along with their > > latencies can also be monitored. Address Translation Services(ATS)event= s > > such as ATS Translation, ATS Page Request, ATS Invalidation along with > > their corresponding latencies are also supported. > > > > The performance counters are 64 bits wide. > > > > For instance, > > perf stat -e ib_tlp_pr > > tracks the inbound posted TLPs for the workload. > > > > Signed-off-by: Gowthami Thiagarajan > > --- > > v2->v3 changes: > > - Dropped device tree support as the acpi table based probing is used. >=20 > So people using DT cannot use this driver? Can they use the PCIe > interface? >=20 > There does not appear to be any ACPI binding, it is not reading any > properties from ACPI tables etc. So the DT binding should be > trivial... The ACPI bindings are present in the driver. Have the ACPI ID MRVL000E tied= here and the resources are fetched from the ACPI table. static const struct acpi_device_id pem_pmu_acpi_match[] =3D { {"MRVL000E", 0}, {}, }; MODULE_DEVICE_TABLE(acpi, pem_pmu_acpi_match); base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); >=20 > > index 000000000000..d4175483b982 > > --- /dev/null > > +++ b/drivers/perf/marvell_pem_pmu.c > > @@ -0,0 +1,428 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Marvell PEM(PCIe RC) Performance Monitor Driver > > + * > > + * Copyright (C) 2024 Marvell. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include >=20 > Why do you need these header files? I don't see any calls to of_ > functions. >=20 These header files are not needed. I will remove them in the next version. > > +static int pem_perf_probe(struct platform_device *pdev) > > +{ > > + struct pem_pmu *pem_pmu; > > + struct resource *res; > > + void __iomem *base; > > + char *name; > > + int ret; > > + > > + pem_pmu =3D devm_kzalloc(&pdev->dev, sizeof(*pem_pmu), GFP_KERNEL); > > + if (!pem_pmu) > > + return -ENOMEM; > > + > > + pem_pmu->dev =3D &pdev->dev; > > + platform_set_drvdata(pdev, pem_pmu); > > + > > + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); > > + if (IS_ERR(base)) > > + return PTR_ERR(base); > > + > > + pem_pmu->base =3D base; > > + > > + pem_pmu->pmu =3D (struct pmu) { > > + .module =3D THIS_MODULE, > > + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, > > + .task_ctx_nr =3D perf_invalid_context, > > + .attr_groups =3D pem_perf_attr_groups, > > + .event_init =3D pem_perf_event_init, > > + .add =3D pem_perf_event_add, > > + .del =3D pem_perf_event_del, > > + .start =3D pem_perf_event_start, > > + .stop =3D pem_perf_event_stop, > > + .read =3D pem_perf_event_update, > > + }; > > + > > + /* Choose this cpu to collect perf data */ > > + pem_pmu->cpu =3D raw_smp_processor_id(); > > + > > + name =3D devm_kasprintf(pem_pmu->dev, GFP_KERNEL, "mrvl_pcie_rc_pmu_%= llx", > > + res->start); > > + if (!name) > > + return -ENOMEM; > > + > > + cpuhp_state_add_instance_nocalls > > + (CPUHP_AP_PERF_ARM_MARVELL_PEM_ONLINE, > > + &pem_pmu->node); > > + > > + ret =3D perf_pmu_register(&pem_pmu->pmu, name, -1); > > + if (ret) > > + goto error; > > + > > + pr_info("Marvell PEM(PCIe RC) PMU Driver for pem@%llx\n", res->start)= ; >=20 > Please don't spam the kernel log like this. Will get this message removed. >=20 > Andrew