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Date: Wed, 03 Apr 2024 09:35:47 +0200
Message-Id: <D0ABCBUEV6ZD.1TDS2WSEH48DY@kernel.org>
Cc: "Nishanth Menon" <nm@ti.com>, "Vignesh Raghavendra" <vigneshr@ti.com>,
 "Tero Kristo" <kristo@kernel.org>, "Rob Herring" <robh@kernel.org>,
 "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley"
 <conor+dt@kernel.org>, <linux-arm-kernel@lists.infradead.org>,
 <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
From: "Michael Walle" <mwalle@kernel.org>
To: "Francesco Dolcini" <francesco@dolcini.it>
Subject: Re: [PATCH] arm64: dts: ti: k3-j722s: Disable ethernet ports by
 default
References: <20240402151802.3803708-1-mwalle@kernel.org>
 <20240402165824.GA32125@francesco-nb>
In-Reply-To: <20240402165824.GA32125@francesco-nb>
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Hi Francesco,

On Tue Apr 2, 2024 at 6:58 PM CEST, Francesco Dolcini wrote:
> On Tue, Apr 02, 2024 at 05:18:02PM +0200, Michael Walle wrote:
> > Device tree best practice is to disable any external interface in the
> > dtsi and just enable them if needed in the device tree. Thus, disable
> > both ethernet ports by default and just enable the one used by the EVM
> > in its device tree.
> >=20
> > There is no functional change.
> >=20
> > Signed-off-by: Michael Walle <mwalle@kernel.org>
> > ---
> > This should also be true for all the other SoCs. But I don't wanted to
> > touch all the (older) device trees. j722s is pretty new, so there we
> > should get it right.
> > ---
> >  arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 5 +----
> >  arch/arm64/boot/dts/ti/k3-j722s.dtsi    | 8 ++++++++
> >  2 files changed, 9 insertions(+), 4 deletions(-)
> >=20
> > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/=
dts/ti/k3-j722s-evm.dts
> > index d045dc7dde0c..afe7f68e6a4b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> > @@ -224,14 +224,11 @@ cpsw3g_phy0: ethernet-phy@0 {
> >  };
> > =20
> >  &cpsw_port1 {
> > +	status =3D "okay";
>
> status should be the last property, according to the dts coding guideline=
s.

Thanks for pointing that out. There is
devicetree/bindings/dts-coding-style.rst, which is in fact new to
me. Up until now, I was under the impression that how this is
handled is up to the maintainer of the SoC. I know that for the NXP
Layerscape for example, the maintainer will have an eye esp. for
that. But here it seems kinda random/all over the place. That being
said, I tried to be consistent with the other cpsw* nodes.

Anyway, I'll change it to come last.

> >  	phy-mode =3D "rgmii-rxid";
> >  	phy-handle =3D <&cpsw3g_phy0>;
> >  };

-michael

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