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Wed, 3 Apr 2024 10:44:22 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 3 Apr 2024 03:44:18 -0700 Date: Wed, 3 Apr 2024 16:14:14 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , Subject: Re: [PATCH v6 1/6] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Message-ID: References: <20240402103406.3638821-1-quic_varada@quicinc.com> <20240402103406.3638821-2-quic_varada@quicinc.com> <1a6fccd3-452c-423f-b73e-cef5f9d01633@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1a6fccd3-452c-423f-b73e-cef5f9d01633@linaro.org> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k7ycNh9ZqvOdxgEBzoJVFehihnn-Yjlh X-Proofpoint-ORIG-GUID: k7ycNh9ZqvOdxgEBzoJVFehihnn-Yjlh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_09,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 malwarescore=0 bulkscore=0 impostorscore=0 mlxlogscore=698 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404030074 On Wed, Apr 03, 2024 at 09:09:15AM +0200, Krzysztof Kozlowski wrote: > On 02/04/2024 12:34, Varadarajan Narayanan wrote: > > +#define ICC_NSSNOC_NSSCC 10 > > +#define ICC_NSSNOC_SNOC_0 11 > > +#define ICC_NSSNOC_SNOC_1 12 > > +#define ICC_NSSNOC_PCNOC_1 13 > > +#define ICC_NSSNOC_QOSGEN_REF 14 > > +#define ICC_NSSNOC_TIMEOUT_REF 15 > > +#define ICC_NSSNOC_XO_DCD 16 > > +#define ICC_NSSNOC_ATB 17 > > +#define ICC_MEM_NOC_NSSNOC 18 > > +#define ICC_NSSNOC_MEMNOC 19 > > +#define ICC_NSSNOC_MEM_NOC_1 20 > > + > > +#define ICC_NSSNOC_PPE 0 > > +#define ICC_NSSNOC_PPE_CFG 1 > > +#define ICC_NSSNOC_NSS_CSR 2 > > +#define ICC_NSSNOC_IMEM_QSB 3 > > +#define ICC_NSSNOC_IMEM_AHB 4 > > + > > +#define MASTER(x) ((ICC_ ## x) * 2) > > +#define SLAVE(x) (MASTER(x) + 1) > > You already received comment to make your bindings consistent with other > Qualcomm bindings. Now you repeat the same mistake. > > No, that is neither consistent nor greppble. Sorry. Have restored the naming and posted v7. Kindly take a look. Thanks Varada