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Date: Tue, 2 Apr 2024 22:03:39 -0400
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Cc: yazen.ghannam@amd.com, linux-kernel@vger.kernel.org,
 avadhut.naik@amd.com, muralidhara.mk@amd.com
Subject: Re: [PATCH v2 1/4] RAS/AMD/ATL: Read DRAM hole base early
To: John Allen <john.allen@amd.com>, bp@alien8.de,
 linux-edac@vger.kernel.org, tony.luck@intel.com
References: <20240327185222.98998-1-john.allen@amd.com>
 <20240327185222.98998-2-john.allen@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>
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 =?utf-8?B?QlBtcHZqYUIvVlBhM3dUWGxzSFNXUGZQb3RKWlpTZ1g0ZGg0Q093V2JVTDJN?=
 =?utf-8?B?MVVnUFFUcE1BYTlvTDl3RjdWYVU1R2RTOUZPZmc4MU8zUDYzOXdQSkdONm1l?=
 =?utf-8?B?c3ZwSTAxWHVrN1EvNE0zUEg1MloxcXZoVHNuWi9FREc1TEtsemYvQ2FycGoy?=
 =?utf-8?B?KzR0SE5rQnNtdHJWeDF3TThpQVhMWFJKY3hFZVp3N2JSSWR6Sk1DRkhZUmpj?=
 =?utf-8?B?ejlTS2NsZnNrakkvcW0wM3lLSzlDYlVCOW5sM0dxbTJKWG1ON0Q5akRDWkRN?=
 =?utf-8?B?dTNHVGIwTTcxV2hjSWlpbmxMT1NscE9JUXdyelZBRnM1Y1BTTFF0eTZvQ2p3?=
 =?utf-8?B?SlE2aE5kT2VkckxiOWJ3bi9DYTJKeFMveUEvcGhVMTRlWU9aSkRVREJKNUQz?=
 =?utf-8?B?NTlrK3dZUE5rRWZFN3lTSEEzaDloZ05DK3F0aURLQklLRlVYWW8rS0RZWUIv?=
 =?utf-8?B?bFVHT2oweWdjSTVIY0U0blZ2ei94V0ZXMWp4alg5Smw4MzhXZmE0VERoZG1B?=
 =?utf-8?B?TFdkWm5YalZkKzdkTzhiRU91d2gyUTU3NHJua3JTRGtjZkZUQzdsQnlxOHFJ?=
 =?utf-8?B?RlcyQTlBRFhOSTJjT2RQclBNS2JaNWR5TVFQWEdyTzlZVk5OUkl0VDZlSHJH?=
 =?utf-8?B?elpZVzhMellwL1NMVFhTeXdXOU51Q29EMUVQcWt0eGQ1eG5oVzlaUGxRVG9n?=
 =?utf-8?B?VyswaWxWdjdKMFRCbmZzT0ZmUWVEUDAza3o5RkQrSEs1U044T0UzWHo3T1V3?=
 =?utf-8?B?SlcrWDhXZjBYVTVBeUxDZXp1Y28rRFZ2SHJ3VGN6ZllCTXNwbXo1b1Exdy9U?=
 =?utf-8?B?eDJ1dFJza05JNHpTV2xSQnNBR2FUK1FWN1VqTTR6VU5oS3dyRGJWM2VhVzBE?=
 =?utf-8?B?RjVCWVFzWDhJZzVVOTV5dlN6Z1ZTdmRTOHI2TVZzME9LVGhlL1RPTU5wODBY?=
 =?utf-8?B?UFBqNVN3Um1TSmo5V3dWT29JdmptQzRoSDBjdEZTK3FJQS85Z2l0U1p5ZStu?=
 =?utf-8?B?WG9jQ2IxcTQydmFsS1dPUE53M3dtSG9naktUQzB2dHNqZlZOYlZsZnhaajhh?=
 =?utf-8?B?a1JGcnJxZlFSZ2RyRmlrb3pnZkZGWElIZFFaS2d6Z3Nwb01rN093L3dYbmZP?=
 =?utf-8?B?MmhJM3dYR21XVkNTQ3NhNjlPRDk5ejUxQzFQYnZsKysrNUErUUU0azlkMnZz?=
 =?utf-8?B?cm5YMCs2VmVWRTlNejluTmxFa0l2Zk1OdU0vcUl5aEE0SXRjRXhGS3lwQ2tj?=
 =?utf-8?B?a1ErbDFBaFFrYnhteXQxNjJsWUhUaFlDQnVrRWNaTXg2T1QzcVZTT3EzTllm?=
 =?utf-8?B?U0F6UVhzK1RNSjljeWxBMC9tanBRYmJHYlBsQVZiNENRa0c3VXp6WTRHc3ZE?=
 =?utf-8?B?ZVVqMHJrck4xdE41amFOOTJ6TGtIYUllNWZFVDZ4czhOWUU0QTdTaGduc0Ev?=
 =?utf-8?B?bFIxdXlpR1IxNWUyUG9KRnBQM2hHLzB2SjB3U1BPbXN0WnRPa24wSk9IYmhu?=
 =?utf-8?B?YnhnUU4xa2JUZHhPUkhKUlhKOVZPMHhSU09wb2JHaHZhMU43NUZYK1NVZ0Np?=
 =?utf-8?B?YkVlUnJxZ28xeUlWZTRJMFFjNU1KcTU0RHJMZU9Ea2RMbFc1QUtmODgxa3RL?=
 =?utf-8?B?cC9vT0svVW50ZXpoeXNPT00rM3NpVjlvSWc2aE9TbnJscVU5ZVZvYkVrYmVt?=
 =?utf-8?B?cXEwMGRBK0JDT0l5cTFXUG90THpLc0RjS3lYRGFkRXdpeXBianJDaUpDRWRB?=
 =?utf-8?B?Nytkb1hNdjRSZ0FyclJrZUNRYlVWNEk1R3VERVhrM1ZtYlF6QVRsdC9QemUy?=
 =?utf-8?B?czRhYWJneXVYUWtxSTBkcFhvVVF3amh2RXo0bWovUExRT1JZMjlTeUVEMWpD?=
 =?utf-8?Q?URYr7FG2+O46vxxx6bqTg43tK?=
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On 3/27/24 14:52, John Allen wrote:
> Read DRAM hole base when constructing the address map as the value will
> not change during run time.
> 
> Signed-off-by: John Allen <john.allen@amd.com>
> ---
> v2:
>    - Fix compilation error. ctx->addr should read ctx->ret_addr.
>    - Improve commit description.
> ---
>   drivers/ras/amd/atl/core.c     | 15 ++-------------
>   drivers/ras/amd/atl/internal.h |  2 ++
>   drivers/ras/amd/atl/system.c   | 21 +++++++++++++++++++++
>   3 files changed, 25 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/ras/amd/atl/core.c b/drivers/ras/amd/atl/core.c
> index 6dc4e06305f7..63513d972c07 100644
> --- a/drivers/ras/amd/atl/core.c
> +++ b/drivers/ras/amd/atl/core.c
> @@ -51,22 +51,11 @@ static bool legacy_hole_en(struct addr_ctx *ctx)
>   
>   static int add_legacy_hole(struct addr_ctx *ctx)
>   {
> -	u32 dram_hole_base;
> -	u8 func = 0;
> -
>   	if (!legacy_hole_en(ctx))
>   		return 0;
>   
> -	if (df_cfg.rev >= DF4)
> -		func = 7;
> -
> -	if (df_indirect_read_broadcast(ctx->node_id, func, 0x104, &dram_hole_base))
> -		return -EINVAL;
> -
> -	dram_hole_base &= DF_DRAM_HOLE_BASE_MASK;
> -
> -	if (ctx->ret_addr >= dram_hole_base)
> -		ctx->ret_addr += (BIT_ULL(32) - dram_hole_base);
> +	if (ctx->ret_addr >= df_cfg.dram_hole_base)
> +		ctx->ret_addr += (BIT_ULL(32) - df_cfg.dram_hole_base);
>   
>   	return 0;
>   }
> diff --git a/drivers/ras/amd/atl/internal.h b/drivers/ras/amd/atl/internal.h
> index 5de69e0bb0f9..1413c8ddc6c5 100644
> --- a/drivers/ras/amd/atl/internal.h
> +++ b/drivers/ras/amd/atl/internal.h
> @@ -132,6 +132,8 @@ struct df_config {
>   	/* Number of DRAM Address maps visible in a Coherent Station. */
>   	u8 num_coh_st_maps;
>   
> +	u32 dram_hole_base;
> +
>   	/* Global flags to handle special cases. */
>   	struct df_flags flags;
>   };
> diff --git a/drivers/ras/amd/atl/system.c b/drivers/ras/amd/atl/system.c
> index 701349e84942..6f6fe24dec81 100644
> --- a/drivers/ras/amd/atl/system.c
> +++ b/drivers/ras/amd/atl/system.c
> @@ -223,6 +223,21 @@ static int determine_df_rev(void)
>   	return -EINVAL;
>   }
>   
> +static int get_dram_hole_base(void)
> +{
> +	u8 func = 0;
> +
> +	if (df_cfg.rev >= DF4)
> +		func = 7;
> +
> +	if (df_indirect_read_broadcast(0, func, 0x104, &df_cfg.dram_hole_base))
> +		return -EINVAL;
> +
> +	df_cfg.dram_hole_base &= DF_DRAM_HOLE_BASE_MASK;
> +
> +	return 0;
> +}
> +
>   static void get_num_maps(void)
>   {
>   	switch (df_cfg.rev) {
> @@ -266,6 +281,7 @@ static void dump_df_cfg(void)
>   
>   	pr_debug("num_coh_st_maps=%u",			df_cfg.num_coh_st_maps);
>   
> +	pr_debug("dram_hole_base=%x",			df_cfg.dram_hole_base);

This should include a "0x" prefix to make clear it is a hex value when
printed.

>   	pr_debug("flags.legacy_ficaa=%u",		df_cfg.flags.legacy_ficaa);
>   	pr_debug("flags.socket_id_shift_quirk=%u",	df_cfg.flags.socket_id_shift_quirk);
>   }
> @@ -282,6 +298,11 @@ int get_df_system_info(void)
>   
>   	get_num_maps();
>   
> +	if (get_dram_hole_base()) {
> +		pr_warn("amd_atl: Failed to read DRAM hole base");
> +		return -EINVAL;
> +	}
> +
>   	dump_df_cfg();
>   
>   	return 0;

With the small change above, this looks good to me.

Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>

Thanks,
Yazen