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AJvYcCXVgw4HAcqLlaCYbgT5rUqBXchuwC4EWE/cmAtss1HncwqL8iH5btdBnAkrtgVHmLHCC4px8JEwAlQCJxZzukKb0FD2YMgRo11oMQvX X-Gm-Message-State: AOJu0Yyy95WRbpRjZCcOQXYqycAk0xbqpXceXTBvf1WjbSlSMqce2BOz 0QBm4uLKKMz6RgG38nu/keT60AJAmC6xcjB3jvYrL8I8mj4oMXZfnbq3s7Jp10PhXR8BCn7XzTH NGXp53xPd08emhBAia50ceq1+l3jL1S2qXaqtRA== X-Received: by 2002:a25:8692:0:b0:dc6:d102:a0bb with SMTP id z18-20020a258692000000b00dc6d102a0bbmr1904903ybk.24.1712156448065; Wed, 03 Apr 2024 08:00:48 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240403-msm-drm-dsc-dsi-video-upstream-v1-0-db5036443545@linaro.org> <20240403-msm-drm-dsc-dsi-video-upstream-v1-1-db5036443545@linaro.org> In-Reply-To: From: Dmitry Baryshkov Date: Wed, 3 Apr 2024 18:00:36 +0300 Message-ID: Subject: Re: [PATCH v3 1/6] drm/msm/dpu: fix video mode DSC for DSI To: Jun Nie Cc: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Vinod Koul , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jonathan Marek Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 3 Apr 2024 at 17:44, Jun Nie wrote: > > Dmitry Baryshkov =E4=BA=8E2024=E5=B9=B44=E6= =9C=883=E6=97=A5=E5=91=A8=E4=B8=89 17:57=E5=86=99=E9=81=93=EF=BC=9A > > > > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote: > > > > > > From: Jonathan Marek > > > > > > Add necessary DPU timing and control changes for DSC to work with DSI > > > video mode. > > > > > > Signed-off-by: Jonathan Marek > > > Signed-off-by: Jun Nie > > > --- > > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +++++++++ > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 ++++++++ > > > 2 files changed, 17 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/d= rivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > index d9e7dbf0499c..c7b009a60b63 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > @@ -115,6 +115,15 @@ static void drm_mode_to_intf_timing_params( > > > timing->h_front_porch =3D timing->h_front_porch >> 1; > > > timing->hsync_pulse_width =3D timing->hsync_pulse_wid= th >> 1; > > > } > > > + > > > + /* > > > + * for DSI, if compression is enabled, then divide the horizo= nal active > > > + * timing parameters by compression ratio. > > > + */ > > > + if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->comp= ression_en) { > > > + timing->width =3D timing->width / 3; /* XXX: don't as= sume 3:1 compression ratio */ > > > + timing->xres =3D timing->width; > > > + } > > > } > > > > > > static u32 get_horizontal_total(const struct dpu_hw_intf_timing_para= ms *timing) > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_intf.c > > > index 965692ef7892..079efb48db05 100644 > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > > @@ -167,6 +167,14 @@ static void dpu_hw_intf_setup_timing_engine(stru= ct dpu_hw_intf *ctx, > > > intf_cfg2 |=3D INTF_CFG2_DATABUS_WIDEN; > > > > > > data_width =3D p->width; > > > + if (p->wide_bus_en && !dp_intf) > > > + data_width =3D p->width >> 1; > > > > How is wide_bus relevant to the DSC case? > > Is there a need for the Fixes tag? > > 48bit bus width should be used when DSC is enabled. Without the > widebus configuration, > a lot dsi error happens as below in DSC case. > [ 206.275992] dsi_err_worker: status=3D4 Still, separate patch please. > > For the Fixes tag, the previous patch mentioned to enable the widebus > mode for any DSC case. So it is fair to add the tag. Yes, please. > > > > > + > > > + if (p->compression_en) > > > + intf_cfg2 |=3D INTF_CFG2_DCE_DATA_COMPRESS; > > > + > > > + if (p->compression_en && dp_intf) > > > + DPU_ERROR("missing adjustments for DSC+DP\n"); > > > > > > hsync_data_start_x =3D hsync_start_x; > > > hsync_data_end_x =3D hsync_start_x + data_width - 1; > > > > > > -- > > > 2.34.1 > > > > > > > > > -- > > With best wishes > > Dmitry --=20 With best wishes Dmitry