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Fri, 5 Apr 2024 00:08:42 GMT Received: from [10.71.109.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 4 Apr 2024 17:08:41 -0700 Message-ID: <5b7c83f8-2b51-64d8-04c4-49a2047818a5@quicinc.com> Date: Thu, 4 Apr 2024 17:08:40 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH] phy: qcom: qmp-combo: Fix register base for QSERDES_DP_PHY_MODE Content-Language: en-US To: Stephen Boyd , Vinod Koul , "Kishon Vijay Abraham I" CC: , , , Konrad Dybcio , , , "Douglas Anderson" , Dmitry Baryshkov , Neil Armstrong , Abel Vesa , Steev Klimaszewski , "Johan Hovold" , Bjorn Andersson References: <20240405000111.1450598-1-swboyd@chromium.org> From: Abhinav Kumar In-Reply-To: <20240405000111.1450598-1-swboyd@chromium.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MqIBCu0PLoWjjOkhmGTBls-XToid3Ogy X-Proofpoint-GUID: MqIBCu0PLoWjjOkhmGTBls-XToid3Ogy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-04_21,2024-04-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1011 adultscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404040172 On 4/4/2024 5:01 PM, Stephen Boyd wrote: > The register base that was used to write to the QSERDES_DP_PHY_MODE > register was 'dp_dp_phy' before commit 815891eee668 ("phy: > qcom-qmp-combo: Introduce orientation variable"). There isn't any > explanation in the commit why this is changed, so I suspect it was an > oversight or happened while being extracted from some other series. > Oddly the value being 0x4c or 0x5c doesn't seem to matter for me, so I > suspect this is dead code, but that can be fixed in another patch. It's > not good to write to the wrong register space, and maybe some other > version of this phy relies on this. > > Cc: Douglas Anderson > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Cc: Neil Armstrong > Cc: Abel Vesa > Cc: Steev Klimaszewski > Cc: Johan Hovold > Cc: Bjorn Andersson > Fixes: 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable") > Signed-off-by: Stephen Boyd > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Yes I dont know why the commit 815891eee668 ("phy: qcom-qmp-combo: Introduce orientation variable") changed the base in below code. Certainly looks like a bug to me because we should be writing to DP_PHY_MODE which is at an offset 0x1c from the dp_phy base. Hence, this LGTM, Reviewed-by: Abhinav Kumar