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[2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id f4-20020a50d544000000b00568631aebb7si7237879edj.606.2024.04.03.22.05.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 22:05:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-130890-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel+bounces-130890-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-130890-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 1E9F71F262CC for ; Thu, 4 Apr 2024 05:05:49 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4D61C7580D; Thu, 4 Apr 2024 05:01:23 +0000 (UTC) Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B15024642A; Thu, 4 Apr 2024 05:01:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=153.127.30.23 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206882; cv=none; b=pV+EtgDiCDuq0lj6MrPOoUfr4984T6rNyfO+GATs9Z0tF1ULAr6qArc9cSyaQQ8DyZ9LtEVYl6TPXU0lrrn9zn3Mx1kWo/2v8Ls2uQEq/fSe+P6WVeSXov70ompxZCTrbcAelpP5Gt6erOo0QDViSXoNtEwLQXorO/ZL1YCnurc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712206882; c=relaxed/simple; bh=RfBIVerSVY5ro3iClkCuqoyBsbZfPpMYmGiZieoqKAU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RRk21OWuKexCZxDtqlzKiqDwdw9rsOwzqKIphxEFxJTjbWltrUch6Q8n83viHGFHE/Urd1aRo1O4FaZni45LPhy3/NwDJFqX/vGB1Vd2lzC+gAhsZLM83yDozF+GqTCMjqIUsc3W20Mj2gvlntLHtG1HLSLmTvX1pMyjYUheGVY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp; spf=fail smtp.mailfrom=users.sourceforge.jp; arc=none smtp.client-ip=153.127.30.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id AEDF81C0B3E; Thu, 4 Apr 2024 14:01:18 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Shawn Guo , Sebastian Reichel , Chris Morgan , Linus Walleij , Arnd Bergmann , David Rientjes , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Vlastimil Babka , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Javier Martinez Canillas , Guo Ren , Azeem Shaikh , Max Filippov , Jonathan Corbet , Jacky Huang , Herve Codina , Manikanta Guntupalli , Anup Patel , Biju Das , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [PATCH v7 23/37] dt-bindings: display: sm501 register definition helper Date: Thu, 4 Apr 2024 14:00:02 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Miscellaneous Timing and Miscellaneous Control registers definition. Signed-off-by: Yoshinori Sato --- include/dt-bindings/display/sm501.h | 76 +++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 include/dt-bindings/display/sm501.h diff --git a/include/dt-bindings/display/sm501.h b/include/dt-bindings/display/sm501.h new file mode 100644 index 000000000000..a6c6943642e4 --- /dev/null +++ b/include/dt-bindings/display/sm501.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DT_BINDING_DISPALY_SM501__ +#define __DT_BINDING_DISPALY_SM501__ + +/* Miscellaneous Conntrol */ +#define SM501_MISC_CONTROL_PAD_24 0 +#define SM501_MISC_CONTROL_PAD_12 1 +#define SM501_MISC_CONTROL_PAD_8 2 + +#define SM501_MISC_CONTROL_USBCLK_XTAL 0 +#define SM501_MISC_CONTROL_USBCLK_96MHZ 1 +#define SM501_MISC_CONTROL_USBCLK_48MHZ 2 + +#define SM501_MISC_CONTROL_RFSH_8US 0 +#define SM501_MISC_CONTROL_RFSH_16US 1 +#define SM501_MISC_CONTROL_RFSH_32US 2 +#define SM501_MISC_CONTROL_RFSH_64US 3 + +#define SM501_MISC_CONTROL_HOLD_EMPTY 0 +#define SM501_MISC_CONTROL_HOLD_8TR 1 +#define SM501_MISC_CONTROL_HOLD_16TR 2 +#define SM501_MISC_CONTROL_HOLD_24TR 3 +#define SM501_MISC_CONTROL_HOLD_32TR 4 + +/* Miscellaneous timing */ +#define SM501_MISC_TIMING_EX_HOLD_0 0 +#define SM501_MISC_TIMING_EX_HOLD_16 1 +#define SM501_MISC_TIMING_EX_HOLD_32 2 +#define SM501_MISC_TIMING_EX_HOLD_48 3 +#define SM501_MISC_TIMING_EX_HOLD_64 4 +#define SM501_MISC_TIMING_EX_HOLD_80 5 +#define SM501_MISC_TIMING_EX_HOLD_96 6 +#define SM501_MISC_TIMING_EX_HOLD_112 7 +#define SM501_MISC_TIMING_EX_HOLD_128 8 +#define SM501_MISC_TIMING_EX_HOLD_144 9 +#define SM501_MISC_TIMING_EX_HOLD_160 10 +#define SM501_MISC_TIMING_EX_HOLD_176 11 +#define SM501_MISC_TIMING_EX_HOLD_192 12 +#define SM501_MISC_TIMING_EX_HOLD_208 13 +#define SM501_MISC_TIMING_EX_HOLD_224 14 +#define SM501_MISC_TIMING_EX_HOLD_240 15 + +#define SM501_MISC_TIMING_XC_INTERNAL 0 +#define SM501_MISC_TIMING_XC_HCLK 1 +#define SM501_MISC_TIMING_XC_GPIO 2 + +#define SM501_MISC_TIMING_SM_DIV1 0 +#define SM501_MISC_TIMING_SM_DIV2 1 +#define SM501_MISC_TIMING_SM_DIV4 2 +#define SM501_MISC_TIMING_SM_DIV8 3 +#define SM501_MISC_TIMING_SM_DIV16 4 +#define SM501_MISC_TIMING_SM_DIV32 5 +#define SM501_MISC_TIMING_SM_DIV64 6 +#define SM501_MISC_TIMING_SM_DIV128 7 +#define SM501_MISC_TIMING_SM_DIV3 8 +#define SM501_MISC_TIMING_SM_DIV6 9 +#define SM501_MISC_TIMING_SM_DIV12 10 +#define SM501_MISC_TIMING_SM_DIV24 11 +#define SM501_MISC_TIMING_SM_DIV48 12 +#define SM501_MISC_TIMING_SM_DIV96 13 +#define SM501_MISC_TIMING_SM_DIV192 14 +#define SM501_MISC_TIMING_SM_DIV384 15 + +#define SM501_MISC_TIMING_DIV336MHZ 0 +#define SM501_MISC_TIMING_DIV288MHZ 1 +#define SM501_MISC_TIMING_DIV240MHZ 2 +#define SM501_MISC_TIMING_DIV192MHZ 3 + +#define SM501_MISC_TIMING_DELAY_NONE 0 +#define SM501_MISC_TIMING_DELAY_0_5 1 +#define SM501_MISC_TIMING_DELAY_1_0 2 +#define SM501_MISC_TIMING_DELAY_1_5 3 +#define SM501_MISC_TIMING_DELAY_2_0 4 +#define SM501_MISC_TIMING_DELAY_2_5 5 + +#endif -- 2.39.2