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AJvYcCW/vwtHBCmIoXsN+DrRRqQGA189mbbM2dxTISep/5ucBRk1OvZI/v9cQTLZvD2Wyw4sgXOQKs8xPbCjWdfky943x1Q8XoXR3/brY680 X-Gm-Message-State: AOJu0YwOWkG0NVkdVULIY9gsw6qDssTsu01fzBFxyoYnKJGRagzG2arj qpTtCMR1uwvZtVIh4lzBtZD6rRB5iQFLqSc0HZtt/OJQC5QzI52zIdFsbmhJcNHEmtOeihTmsDw X6DV5ZywwqjnPU09GdDVtlqCI8FWsPDlppMrSNg== X-Received: by 2002:a25:dc92:0:b0:dcc:6894:4ac0 with SMTP id y140-20020a25dc92000000b00dcc68944ac0mr207083ybe.20.1712285700487; Thu, 04 Apr 2024 19:55:00 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240404234345.1446300-1-swboyd@chromium.org> In-Reply-To: <20240404234345.1446300-1-swboyd@chromium.org> From: Dmitry Baryshkov Date: Fri, 5 Apr 2024 05:54:49 +0300 Message-ID: Subject: Re: [PATCH] phy: qcom: qmp-combo: Fix VCO div offset on v3 To: Stephen Boyd Cc: Vinod Koul , Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-msm@vger.kernel.org, Konrad Dybcio , Bjorn Andersson , linux-phy@lists.infradead.org, Neil Armstrong , freedreno@lists.freedesktop.org, Douglas Anderson , Abhinav Kumar Content-Type: text/plain; charset="UTF-8" On Fri, 5 Apr 2024 at 02:43, Stephen Boyd wrote: > > Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to > setup clocks") changed the offset that is used to write to > DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to > QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different > between v3 and v4 phys: > > #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 > #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 > > meaning that we write the wrong register on v3 phys now. Add another > generic register to 'regs' and use it here instead of a version specific > define to fix this. > > This was discovered after Abhinav looked over register dumps with me > from sc7180 Trogdor devices that started failing to light up the > external display with v6.6 based kernels. It turns out that some > monitors are very specific about their link clk frequency and if the > default power on reset value is still there the monitor will show a > blank screen or a garbled display. Other monitors are perfectly happy to > get a bad clock signal. > > Cc: Douglas Anderson > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup clocks") > Signed-off-by: Stephen Boyd > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry