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Fri, 5 Apr 2024 06:01:08 GMT Received: from [10.218.5.19] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 4 Apr 2024 23:01:02 -0700 Message-ID: <03f8d2ee-2467-48aa-9b76-06eb13202b8c@quicinc.com> Date: Fri, 5 Apr 2024 11:30:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 6/6] arm64: dts: qcom: sm8650: Add video and camera clock controllers To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Vladimir Zapolskiy , , , , , Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-7-quic_jkona@quicinc.com> <008d574f-9c9e-48c6-b64e-89fb469cbde4@quicinc.com> <8a5a3cf8-5b4f-487f-ad91-00499509f8ec@quicinc.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HmuYKecfWjlKZSgXwRfjOxxcbIuBOWnQ X-Proofpoint-ORIG-GUID: HmuYKecfWjlKZSgXwRfjOxxcbIuBOWnQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-05_05,2024-04-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404050042 On 4/4/2024 9:35 PM, Dmitry Baryshkov wrote: > On Thu, 4 Apr 2024 at 13:06, Jagadeesh Kona wrote: >> >> >> >> On 4/4/2024 11:00 AM, Dmitry Baryshkov wrote: >>> On Thu, 4 Apr 2024 at 08:13, Jagadeesh Kona wrote: >>>> >>>> >>>> >>>> On 4/3/2024 9:24 PM, Dmitry Baryshkov wrote: >>>>> On Wed, 3 Apr 2024 at 10:16, Jagadeesh Kona wrote: >>>>>> >>>>>> >>>>>> >>>>>> On 3/25/2024 11:38 AM, Jagadeesh Kona wrote: >>>>>>> >>>>>>> >>>>>>> On 3/21/2024 6:43 PM, Dmitry Baryshkov wrote: >>>>>>>> On Thu, 21 Mar 2024 at 11:27, Jagadeesh Kona >>>>>>>> wrote: >>>>>>>>> >>>>>>>>> Add device nodes for video and camera clock controllers on Qualcomm >>>>>>>>> SM8650 platform. >>>>>>>>> >>>>>>>>> Signed-off-by: Jagadeesh Kona >>>>>>>>> --- >>>>>>>>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 28 ++++++++++++++++++++++++++++ >>>>>>>>> 1 file changed, 28 insertions(+) >>>>>>>>> >>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> index 32c0a7b9aded..d862aa6be824 100644 >>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>>>>>>> @@ -4,6 +4,8 @@ >>>>>>>>> */ >>>>>>>>> >>>>>>>>> #include >>>>>>>>> +#include >>>>>>>>> +#include >>>>>>>>> #include >>>>>>>>> #include >>>>>>>>> #include >>>>>>>>> @@ -3110,6 +3112,32 @@ opp-202000000 { >>>>>>>>> }; >>>>>>>>> }; >>>>>>>>> >>>>>>>>> + videocc: clock-controller@aaf0000 { >>>>>>>>> + compatible = "qcom,sm8650-videocc"; >>>>>>>>> + reg = <0 0x0aaf0000 0 0x10000>; >>>>>>>>> + clocks = <&bi_tcxo_div2>, >>>>>>>>> + <&gcc GCC_VIDEO_AHB_CLK>; >>>>>>>>> + power-domains = <&rpmhpd RPMHPD_MMCX>; >>>>>>>>> + required-opps = <&rpmhpd_opp_low_svs>; >>>>>>>> >>>>>>>> The required-opps should no longer be necessary. >>>>>>>> >>>>>>> >>>>>>> Sure, will check and remove this if not required. >>>>>> >>>>>> >>>>>> I checked further on this and without required-opps, if there is no vote >>>>>> on the power-domain & its peer from any other consumers, when runtime >>>>>> get is called on device, it enables the power domain just at the minimum >>>>>> non-zero level. But in some cases, the minimum non-zero level of >>>>>> power-domain could be just retention and is not sufficient for clock >>>>>> controller to operate, hence required-opps property is needed to specify >>>>>> the minimum level required on power-domain for this clock controller. >>>>> >>>>> In which cases? If it ends up with the retention vote, it is a bug >>>>> which must be fixed. >>>>> >>>> >>>> The minimum non-zero level(configured from bootloaders) of MMCX is >>>> retention on few chipsets but it can vary across the chipsets. Hence to >>>> be on safer side from our end, it is good to have required-opps in DT to >>>> specify the minimum level required for this clock controller. >>> >>> We are discussing sm8650, not some abstract chipset. Does it list >>> retention or low_svs as a minimal level for MMCX? >>> >> >> Actually, the minimum level for MMCX is external to the clock >> controllers. > > Yes, it comes from cmd-db > >> But the clock controller requires MMCX to be atleast at >> lowsvs for it to be functional. > > Correct > >> Hence we need to keep required-opps to >> ensure the same without relying on the actual minimum level for MMCX. > > And this is not correct. There is no need for the DT to be redundant. > I plan to send patches removing the existing required-opps when they > are not required. > I agree this is not required if cmd-db minimum level is already at lowsvs. But since MMCX running at lowsvs is a mandatory requirement for clock controller to operate, I believe it is good to have required-opps to ensure we meet this requirement in all cases, rather than relying on the cmd-db minimum level which we have no control over. Thanks, Jagadeesh