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From: Andrii Nakryiko <andrii.nakryiko@gmail.com>
Date: Fri, 5 Apr 2024 11:10:41 -0700
Message-ID: <CAEf4Bza3s4u5kX3AFDWd6-JGjfkhwfakc8_AKH52L7517Q8QGQ@mail.gmail.com>
Subject: Re: [PATCH bpf-next] arm64, bpf: add internal-only MOV instruction to
 resolve per-CPU addrs
To: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Cc: Puranjay Mohan <puranjay12@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, 
	Will Deacon <will@kernel.org>, Alexei Starovoitov <ast@kernel.org>, Daniel Borkmann <daniel@iogearbox.net>, 
	Andrii Nakryiko <andrii@kernel.org>, Martin KaFai Lau <martin.lau@linux.dev>, 
	Eduard Zingerman <eddyz87@gmail.com>, Song Liu <song@kernel.org>, 
	Yonghong Song <yonghong.song@linux.dev>, John Fastabend <john.fastabend@gmail.com>, 
	KP Singh <kpsingh@kernel.org>, Stanislav Fomichev <sdf@google.com>, Hao Luo <haoluo@google.com>, 
	Jiri Olsa <jolsa@kernel.org>, Zi Shen Lim <zlim.lnx@gmail.com>, Xu Kuohai <xukuohai@huawei.com>, 
	Florent Revest <revest@chromium.org>, 
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org>, 
	bpf <bpf@vger.kernel.org>
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On Fri, Apr 5, 2024 at 8:48=E2=80=AFAM Alexei Starovoitov
<alexei.starovoitov@gmail.com> wrote:
>
> On Fri, Apr 5, 2024 at 2:17=E2=80=AFAM Puranjay Mohan <puranjay12@gmail.c=
om> wrote:
> >
> > Support an instruction for resolving absolute addresses of per-CPU
> > data from their per-CPU offsets. This instruction is internal-only and
> > users are not allowed to use them directly. They will only be used for
> > internal inlining optimizations for now between BPF verifier and BPF
> > JITs.
> >
> > Since commit 7158627686f0 ("arm64: percpu: implement optimised pcpu
> > access using tpidr_el1"), the per-cpu offset for the CPU is stored in
> > the tpidr_el1/2 register of that CPU.
> >
> > To support this BPF instruction in the ARM64 JIT, the following ARM64
> > instructions are emitted:
> >
> > mov dst, src            // Move src to dst, if src !=3D dst
> > mrs tmp, tpidr_el1/2    // Move per-cpu offset of the current cpu in tm=
p.
> > add dst, dst, tmp       // Add the per cpu offset to the dst.
> >
> > If CONFIG_SMP is not defined, then nothing is emitted if src =3D=3D dst=
, and
> > mov dst, src is emitted if dst !=3D src.
> >
> > To measure the performance improvement provided by this change, the
> > benchmark in [1] was used:
> >
> > Before:
> > glob-arr-inc   :   23.597 =C2=B1 0.012M/s
> > arr-inc        :   23.173 =C2=B1 0.019M/s
> > hash-inc       :   12.186 =C2=B1 0.028M/s
> >
> > After:
> > glob-arr-inc   :   23.819 =C2=B1 0.034M/s
> > arr-inc        :   23.285 =C2=B1 0.017M/s
> > hash-inc       :   12.419 =C2=B1 0.011M/s
> >
> > [1] https://github.com/anakryiko/linux/commit/8dec900975ef
>
> You don't see as big of a gain, because bpf_get_smp_processor_id()
> is not inlined yet on arm64.
>

yep, would be nice to add ARM64 and RISC-V support there as well.
Though it feels that supporting this in BPF JIT directly might be
actually easier for RISC-V/ARM64, not sure?

> But even without it I expected bigger gains.
> Could you do 'perf report' before/after ?
> Just want to see what's on top.

I also did `bpftool p d x id <progid>` and `bpftool p d j id <progid>`
to validate expected inlined BPF instructions and jitted code. So it
might be a good idea to do that as well.

Either way, thanks for working on this!

>
> >
> > Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
> > ---
> >  arch/arm64/include/asm/insn.h |  7 +++++++
> >  arch/arm64/lib/insn.c         | 11 +++++++++++
> >  arch/arm64/net/bpf_jit.h      |  6 ++++++
> >  arch/arm64/net/bpf_jit_comp.c | 16 ++++++++++++++++
> >  4 files changed, 40 insertions(+)
> >

[...]