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AJvYcCU1K8FaAXNPMQDJWzchxYMcB56xXD0+BFAVeUCXLSW8Hq6AbjOb/bF2Nzg5IbPI21L2/iTwHU41wCOaZCGxYg9TPbvTtOQamF7xjJPn X-Gm-Message-State: AOJu0YwmaxZ5+5n7M3MZ9sz7A+QFySLDYxyO2amZ8iKke1Bt5KNnaoPI GpZMiAwYzftV2PBkmE9i+MlIw/s8jsFy9/15MEnxYbRB5a+gQFXU4twV3qv2NhlREvWd2S7msQJ Uow== X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a00:188f:b0:6eb:3b8d:dc9b with SMTP id x15-20020a056a00188f00b006eb3b8ddc9bmr368324pfh.3.1712361368118; Fri, 05 Apr 2024 16:56:08 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 5 Apr 2024 16:55:53 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.44.0.478.gd926399ef9-goog Message-ID: <20240405235603.1173076-1-seanjc@google.com> Subject: [PATCH 00/10] KVM: x86: Fix LVTPC masking on AMD CPUs From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Sandipan Das , Jim Mattson , Like Xu Content-Type: text/plain; charset="UTF-8" This is kinda sorta v2 of Sandipan's fix for KVM's incorrect setting of the MASK bit when delivering PMIs through the LVTPC. It's a bit rushed, as I want to get Sandipan's fix applied early next week so that it can make its way to Linus' tree for -rc4. And I didn't want to apply Sandipan's patch as-is, because I'm a little paranoid that the guest CPUID check could be noticeable slow, and it's easy to avoid. My plan is to grab patches 1-2 for 6.9 asap, and let the rest simmer for much, much longer (they are *very* lightly tested). As for why this looks wildy different than Sandipan's compat_vendor idea, when I started looking at KVM's various AMD vs. Intel checks, I realized it makes no sense to support an "unknown" vendor. KVM can't do *nothing*, and so practically speaking, an "unknown" vendor vCPU would actually end up with a weird mix of AMD *and* Intel behavior, not AMD *or* Intel behavior. Sandipan Das (1): KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms Sean Christopherson (9): KVM: x86: Snapshot if a vCPU's vendor model is AMD vs. Intel compatible KVM: x86/pmu: Squash period for checkpointed events based on host HLE/RTM KVM: x86: Apply Intel's TSC_AUX reserved-bit behavior to Intel compat vCPUs KVM: x86: Inhibit code #DBs in MOV-SS shadow for all Intel compat vCPUs KVM: x86: Use "is Intel compatible" helper to emulate SYSCALL in !64-bit KVM: SVM: Emulate SYSENTER RIP/RSP behavior for all Intel compat vCPUs KVM: x86: Allow SYSENTER in Compatibility Mode for all Intel compat vCPUs KVM: x86: Open code vendor_intel() in string_registers_quirk() KVM: x86: Bury guest_cpuid_is_amd_or_hygon() in cpuid.c arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c | 13 ++++++ arch/x86/kvm/cpuid.h | 16 ++------ arch/x86/kvm/emulate.c | 71 ++++++++++----------------------- arch/x86/kvm/kvm_emulate.h | 1 + arch/x86/kvm/lapic.c | 3 +- arch/x86/kvm/mmu/mmu.c | 2 +- arch/x86/kvm/pmu.c | 2 +- arch/x86/kvm/svm/svm.c | 14 +++---- arch/x86/kvm/x86.c | 30 ++++++++------ 10 files changed, 68 insertions(+), 85 deletions(-) base-commit: 8cb4a9a82b21623dbb4b3051dd30d98356cf95bc -- 2.44.0.478.gd926399ef9-goog