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Sat, 6 Apr 2024 01:29:04 GMT Received: from [10.47.206.1] (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 5 Apr 2024 18:29:03 -0700 Message-ID: Date: Fri, 5 Apr 2024 18:29:03 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 6/7] spmi: pmic-arb: Register controller for bus instead of arbiter Content-Language: en-US To: Abel Vesa , Stephen Boyd , Matthias Brugger , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Neil Armstrong , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Srini Kandagatla , Johan Hovold , , , , , References: <20240402-spmi-multi-master-support-v8-0-ce6f2d14a058@linaro.org> <20240402-spmi-multi-master-support-v8-6-ce6f2d14a058@linaro.org> From: David Collins In-Reply-To: <20240402-spmi-multi-master-support-v8-6-ce6f2d14a058@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VTMQSKwVhBh_InbA8xBhyFtuvnMohNnY X-Proofpoint-GUID: VTMQSKwVhBh_InbA8xBhyFtuvnMohNnY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-05_31,2024-04-05_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=967 malwarescore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404060010 On 4/2/24 05:07, Abel Vesa wrote: > +struct spmi_pmic_arb_bus { > + struct spmi_pmic_arb *pmic_arb; > + struct irq_domain *domain; > + void __iomem *intr; > + void __iomem *cnfg; > + struct spmi_controller *spmic; > + u16 base_apid; > + int apid_count; > + u32 *mapping_table; > + DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); > + u16 *ppid_to_apid; > + u16 last_apid; > + struct apid_data *apid_data; > + u16 min_apid; > + u16 max_apid; > + int irq; > +}; .. > struct spmi_pmic_arb { > void __iomem *rd_base; > void __iomem *wr_base; > - void __iomem *intr; > - void __iomem *cnfg; > void __iomem *core; > resource_size_t core_size; > raw_spinlock_t lock; Can you please move "lock" from "struct spmi_pmic_arb" into "struct spmi_pmic_arb_bus" and update its usage in the functions below? The two SPMI buses within PMIC Arbiter v7 operate entirely independently and write to separate sets of registers. As-is, transactions on one bus would unnecessarily block transactions on the other, leading to a performance penalty. > u8 channel; > - int irq; > u8 ee; > - u32 bus_instance; > - u16 min_apid; > - u16 max_apid; > - u16 base_apid; > - int apid_count; > - u32 *mapping_table; > - DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); > - struct irq_domain *domain; > - struct spmi_controller *spmic; > const struct pmic_arb_ver_ops *ver_ops; > - u16 *ppid_to_apid; > - u16 last_apid; > - struct apid_data *apid_data; > int max_periphs; > + struct spmi_pmic_arb_bus *bus; > }; Thanks, David Collins