Received-SPF: pass (google.com: domain of linux-kernel+bounces-134812-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
From: Markus Burri <markus.burri@mt.com>
To: linux-kernel@vger.kernel.org
Cc: Markus Burri <markus.burri@mt.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-rtc@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: [PATCH v1] rtc: pcf2127: configurable power management function
Date: Mon,  8 Apr 2024 07:49:26 +0200
Message-Id: <20240408054926.3994-1-markus.burri@mt.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?musl8BnmQigEcE1n2hNU+w+SOI0NZ2niBJt6qz+Fto6zo0UuPEs01PnLoieO?=
 =?us-ascii?Q?4ee8zhmf6+dOlDYvr9EieZ5zi7gH1NpuMAFZzHcQULTrWR/D9sm1zHZpQqkH?=
 =?us-ascii?Q?0SkUTYEkFk6veku8GvWY08lK8IyWeAZlwxlN/0UfQFMhTOrwJSPgXzzVUbrm?=
 =?us-ascii?Q?vbWUi5YBLVmmopTGR5w+quwxg0206NM6gvFkMnZ9N2fTKa/c7lk4uwlq08I7?=
 =?us-ascii?Q?SNwDsSX6CpxNiCkn/rMDqfC/NhWG0J72L01pWnefdeSAFrLTN6AimPE0qDrE?=
 =?us-ascii?Q?gorRLF1Vktp7NyjIWWJdwPlLnJnFe9ysrCeit0bsvowVDDnI+ME9j2DTi6co?=
 =?us-ascii?Q?+xQohxBh5h+d4YNJVvxQXSus725JW/L9lYDIc/02o4S+o/deAvANktaOQeKK?=
 =?us-ascii?Q?H7wqiwW7YsL/AnvuCYc43/T4Yg/i9y5vykirWPvNT+byDV3LiOLUGlI9mRmy?=
 =?us-ascii?Q?y5TiNY3nfoK2zxR6k3J32wIcfDD10C9XxOtotIOKC+x0HbBNB+QQD8UQmgww?=
 =?us-ascii?Q?zYyapeog3BBu80VteYXu/BckMxwrTIG4ZRGspbAou+cS3uetAizjCS6/9Lwh?=
 =?us-ascii?Q?WMwnklx+LqKta9IfwkCt+JkyAxmnopoYW7c/cVQI3qa3NMH8gD6Gm6Q5fXME?=
 =?us-ascii?Q?iMZOnjcb3l4vK40MG/TFqFGNKKjSyj1OfHxXyyS2EumTV0re+ivVeB1mbipF?=
 =?us-ascii?Q?qRiav9b/zVnobQLZCAe5SJNTwymhDholyPQzd9FCkw3nJP4acVl4D7QZM69H?=
 =?us-ascii?Q?J4CfLpRn/FNrtybepSeNEaHXyS+8HxvoOLRkEXn57lMUA54STNdoszYM3nC9?=
 =?us-ascii?Q?L/VynwxkQmUR3hlnE95yvRiCoU7hohGMCTB54zMjsPlxQArmJ9M78i5u6Ah3?=
 =?us-ascii?Q?B3A8pamjJnInqBATMTAiODkiE1Q2dW/GsjjLAsDYxiPvMsEtGDbTkWMA48NY?=
 =?us-ascii?Q?ETXqYx+dEjLDw6m7ss1vkXoD9SmD1wZh5rLLsBbexVh/gfSGs2yepXKUVs2z?=
 =?us-ascii?Q?ACtqF4SKsN12cVZz8GCeWUNCjx5OHEPFvhlj8c2fBsw/VcEWmWE5xmj4hzjY?=
 =?us-ascii?Q?O/P7Cj791nL/sWlcO1DUw3z7dnK7/EOUzfGUWINHuK8pq5Ro2sJKbL8lGPua?=
 =?us-ascii?Q?jKD+fZL6A3q4U9XEaQHbKKBN3iFZzyVktYD9SyuTjiFsmDVYoAzu63yzug32?=
 =?us-ascii?Q?VBukMi82h1Z4jDuq9sNJFNVsViRMsoQbfyTRJcxLnJ2Fb06Ts4FZ/6rGwmB0?=
 =?us-ascii?Q?hrE5vs0y8gMq8HdDSmrLoMtQJFGeOSZl/K5d42oWUXyXB6qvGYy/5QXQY5Ml?=
 =?us-ascii?Q?wUiAK9MW8F3xR3/I1iR0oDTO2HrwQ+ey4Pysld6QGjC2ZjkJoeq+miOJkmHr?=
 =?us-ascii?Q?DElj+rpB47lhFOKOTKlu6X9pWZzCcsIrkjnzp9kx5VAUGKNM0QcRuYNfDzKB?=
 =?us-ascii?Q?TNOsJBM09sXvsn/9xd/IFTTYSeB3FbAFDqWL/GC/nqdw8A7WMBFj+WiEsBFF?=
 =?us-ascii?Q?x+YTn16agg1IS/Ui3R/qSxPFWEtgtgC9Z7ctqK2TPOPDZXdfptFHXXxCsqw6?=
 =?us-ascii?Q?RJNZC6chmyphz4bEzq4SUU9XZxSHqM5Wf0LSZZCY?=
X-OriginatorOrg: mt.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9fd1067e-e56e-4c6d-ac79-08dc578fabd0
X-MS-Exchange-CrossTenant-AuthSource: DB9PR03MB7513.eurprd03.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2024 05:49:35.5022
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: fb4c0aee-6cd2-482f-a1a5-717e7c02496b
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: DbG4jrouq7LigTWsovp3aR12APw58Pw2AjZs/F/0MFizbUYkhdaSV7aiy6kxsZBtJBrovay701eHL8pbON95SQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8498

In the PCF2131 power management the battery switch-over function is
disabled by default.
After a power cycle the rtc clock is wrong because of that.
Add a device-tree property to configure the power management function
and enable battery switch-over.

Signed-off-by: Markus Burri <markus.burri@mt.com>
---
 .../devicetree/bindings/rtc/nxp,pcf2127.yaml  |  3 +++
 drivers/rtc/rtc-pcf2127.c                     | 22 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
index 2d9fe5a75b06..5ce0ca6dcedc 100644
--- a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml
@@ -30,6 +30,9 @@ properties:
 
   reset-source: true
 
+  pwrmng-function:
+    description: Set power management function for PCF2131
+
 required:
   - compatible
   - reg
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 9c04c4e1a49c..30d56538c11e 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -48,6 +48,7 @@
 #define PCF2127_BIT_CTRL3_BLF			BIT(2)
 #define PCF2127_BIT_CTRL3_BF			BIT(3)
 #define PCF2127_BIT_CTRL3_BTSE			BIT(4)
+#define PCF2131_BIT_CTRL3_PWRMNG_MASK   GENMASK(7, 5)
 /* Time and date registers */
 #define PCF2127_REG_TIME_BASE		0x03
 #define PCF2127_BIT_SC_OSF			BIT(7)
@@ -187,6 +188,7 @@ struct pcf21xx_config {
 	unsigned int has_bit_wd_ctl_cd0:1;
 	unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
 	unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
+	unsigned int has_pwrmng:1; /* PCF2131 supports power management. */
 	u8 reg_time_base; /* Time/date base register. */
 	u8 regs_alarm_base; /* Alarm function base registers. */
 	u8 reg_wd_ctl; /* Watchdog control register. */
@@ -926,6 +928,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
 		.has_bit_wd_ctl_cd0 = 1,
 		.wd_val_reg_readable = 1,
 		.has_int_a_b = 0,
+		.has_pwrmng = 0,
 		.reg_time_base = PCF2127_REG_TIME_BASE,
 		.regs_alarm_base = PCF2127_REG_ALARM_BASE,
 		.reg_wd_ctl = PCF2127_REG_WD_CTL,
@@ -954,6 +957,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
 		.has_bit_wd_ctl_cd0 = 0,
 		.wd_val_reg_readable = 1,
 		.has_int_a_b = 0,
+		.has_pwrmng = 0,
 		.reg_time_base = PCF2127_REG_TIME_BASE,
 		.regs_alarm_base = PCF2127_REG_ALARM_BASE,
 		.reg_wd_ctl = PCF2127_REG_WD_CTL,
@@ -982,6 +986,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
 		.has_bit_wd_ctl_cd0 = 0,
 		.wd_val_reg_readable = 0,
 		.has_int_a_b = 1,
+		.has_pwrmng = 1,
 		.reg_time_base = PCF2131_REG_TIME_BASE,
 		.regs_alarm_base = PCF2131_REG_ALARM_BASE,
 		.reg_wd_ctl = PCF2131_REG_WD_CTL,
@@ -1241,6 +1246,23 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
 		return ret;
 	}
 
+	if (pcf2127->cfg->has_pwrmng) {
+		uint32_t pwrmng;
+		if (!device_property_read_u32(dev, "pwrmng-function", &pwrmng)) {
+			if (!FIELD_FIT(PCF2131_BIT_CTRL3_PWRMNG_MASK, pwrmng)) {
+				dev_err(dev, "invalid power management function\n");
+				return ret;
+			}
+			ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
+						 PCF2131_BIT_CTRL3_PWRMNG_MASK,
+						 FIELD_PREP(PCF2131_BIT_CTRL3_PWRMNG_MASK, pwrmng));
+			if (ret) {
+				dev_err(dev, "%s: pwrmng (ctrl3) failed\n",	__func__);
+				return ret;
+			}
+		}
+	}
+
 	/*
 	 * Enable timestamp functions 1 to 4.
 	 */
-- 
2.39.2