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Mon, 8 Apr 2024 06:54:41 +0000 Received: from BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::6c9f:86e:4b8e:8234]) by BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::6c9f:86e:4b8e:8234%6]) with mapi id 15.20.7452.019; Mon, 8 Apr 2024 06:54:41 +0000 From: "Tian, Kevin" To: Dimitri Sivanich , Thomas Gleixner , Joerg Roedel , Suravee Suthikulpanit , Will Deacon , Robin Murphy , David Woodhouse , Lu Baolu , Mark Rutland , "Peter Zijlstra" , Arnd Bergmann , YueHaibing , "iommu@lists.linux.dev" CC: "linux-kernel@vger.kernel.org" , Steve Wahl , "Anderson, Russ" Subject: RE: [PATCH v2] iommu/vt-d: Allocate DMAR fault interrupts locally Thread-Topic: [PATCH v2] iommu/vt-d: Allocate DMAR fault interrupts locally Thread-Index: AQHae9GlBWpgQbFT6kOw3+M6DonKQrFeC4YA Date: Mon, 8 Apr 2024 06:54:41 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BN9PR11MB5276:EE_|DS7PR11MB6079:EE_ x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74968de2-c015-4fe3-6e7d-08dc5798c41e X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2024 06:54:41.6516 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T6h+7gm0krE+gxprP8wU8n657zBhPgJi4ZUt5a+GS82ByVBM76kPvtzNsFzOHzjaeWyyIrPl/JILj+yXF6wDnQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB6079 X-OriginatorOrg: intel.com > From: Dimitri Sivanich > Sent: Friday, March 22, 2024 4:51 AM >=20 > The Intel IOMMU code currently tries to allocate all DMAR fault interrupt > vectors on the boot cpu. On large systems with high DMAR counts this > results in vector exhaustion, and most of the vectors are not initially > allocated socket local. >=20 > Instead, have a cpu on each node do the vector allocation for the DMARs o= n > that node. The boot cpu still does the allocation for its node during it= s > boot sequence. >=20 > Signed-off-by: Dimitri Sivanich Reviewed-by: Kevin Tian