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From: Marcelo Schmitt <marcelo.schmitt@analog.com>
To: <lars@metafoo.de>, <Michael.Hennerich@analog.com>, <jic23@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>, <marcelo.schmitt1@gmail.com>
CC: <linux-iio@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 0/2] Add support for AD4000 series
Date: Mon, 8 Apr 2024 11:30:50 -0300
Message-ID: <cover.1712585500.git.marcelo.schmitt@analog.com>
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This is more like an RFC patch set since configuration read/write is currently
buggy.

Change log v1 -> v2:
- Took device tree provided by David.
- Dropped ABI additions in favor of device tree properties.
- Set differential IIO channel subtype for differential ADCs.
- Set scan_type shift bits to mask out correct real bits from buffer.
- Added __aligned(8) to buffer timestamp.
- Used union to reduce buffer memory usage for 16-bit devices.
- Used SPI transfer functions rather than SPI message.
- Used c99 style structure initialization.
- Used iio_device_claim_direct_scoped().
- Removed unneeded pointer casts.
- Added other power supplies (VDD and VIO).

Link to v1: https://lore.kernel.org/linux-iio/cover.1711131830.git.marcelo.schmitt@analog.com/

Additional topics:

- Why there is no different handling for the different SPI wiring modes?
It looks like there is no need for different handling of "4-wire" and "3-wire"
modes.
If in "4-wire" (dt default mode), SDI is connected to SPI controller CS and
CNV is active high. We can activate the CNV GPIO then let the SPI controller
bring CS (connected to SDI) down when starting the transfer.
If in "3-wire" (dt single mode), if we have a CNV (active low) GPIO we activate
it and then proceed with with the transfer. If controller CS is connected to
CNV it works the same way.
I'm thinking it's better if we can support these devices in similar way
other SPI ADCs are supported. Does that make sense?
To me, the "3-wire" mode with controller CS to ADC CNV is what most resembles
conventional SPI. The only important distinction is that the
controller must be able to keep ADC SDI line high during conversions.
Although, while the spi-engine implementation provided to me can keep SDI up
during conversions, I'm not sure its a thing all SPI controllers can do.
I tried a raspberry pi 4 some time ago and it was leaving the SDI line low if
no tx buffer was provided. Even with a tx full of 1s the controller would 
bring SDI down between each 8 bits of transfer.
Anyway, single-shot and buffered reads work with the spi-engine controller
with ADC in "3-wire"/single mode with controller CS line connected to ADC CNV
pin which is how I've been testing it.

- Why did not make vref regulator optional?
Other SAR ADCs I've seen needed a voltage reference otherwise they simply
could not provide any reasonable readings. Isn't it preferable to fail rather
than having a device that can't provide reliable data?

- Why did not split into AD and ADAQ patches?
The main difference between AD and ADAQ is the amplifier in front of the ADC.
If only supporting AD, we could probably avoid the scale table since it would
only have two possible values per ADC. But then the handling of span compression
scale would need refactoring to be in the scale table when adding ADAQ.
I'm not excited to implement something knowing it will need rework in the
following patch. Will do if required.

- Span compression and offset.
For non-differential ADCs, enabling the span compression requires an input offset.
Link: https://www.analog.com/media/en/technical-documentation/data-sheets/AD4000-4004-4008.pdf
page 18
and
Link: https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
page 19
I updated the _offset attribute for those ADCs according to span compression
being enabled or not. Is it okay to have an attribute update cause an update to
another one?
Maybe also make the span compression a dt property and have it fixed after probe?

- Configuration register
Despite it doing single-shot and buffered captures, read and writes to the
configuration register are currently buggy. It is as if the register was
"floating". I tried setting up buffers like ad7768-1, adxl355_core, bma220_spi,
bma400_core, and mcp3911.


Thanks,
Marcelo

Marcelo Schmitt (2):
  dt-bindings: iio: adc: Add AD4000
  iio: adc: Add support for AD4000

 .../bindings/iio/adc/adi,ad4000.yaml          | 201 ++++++
 MAINTAINERS                                   |   8 +
 drivers/iio/adc/Kconfig                       |  12 +
 drivers/iio/adc/Makefile                      |   1 +
 drivers/iio/adc/ad4000.c                      | 649 ++++++++++++++++++
 5 files changed, 871 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml
 create mode 100644 drivers/iio/adc/ad4000.c

-- 
2.43.0