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AJvYcCW18QlzzIBU2aTcR90eTu9gad32FqjLCNsqXBaED5vo198a07+C0I9GrdTpEVRIxIP2evtScmxOPydyvxc2xMjPZ5RFZ3f9MZ55Sr5A X-Gm-Message-State: AOJu0YySOwfYTbn1V7sG5cuACYqoIbgv8+mc8cFAINLpz/c54CCpJ3YU AjU/I0kC4x+rrfRPXBJcPYGk+mY+oFC7dMCaZI56q/4azTDmN9UtRG4uRh1M/8aky3RpZ1qrsT9 rygDJdqTA5+Zt3m2uBMWB1Qi/QL4kXK/PSFK6 X-Received: by 2002:ac2:43b6:0:b0:516:c099:e785 with SMTP id t22-20020ac243b6000000b00516c099e785mr6549819lfl.20.1712633983546; Mon, 08 Apr 2024 20:39:43 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240404081635.91412-1-angelogioacchino.delregno@collabora.com> <20240404081635.91412-3-angelogioacchino.delregno@collabora.com> <5e385c2e-6509-4347-96a5-4606b32d20ff@collabora.com> In-Reply-To: <5e385c2e-6509-4347-96a5-4606b32d20ff@collabora.com> From: Chen-Yu Tsai Date: Tue, 9 Apr 2024 11:39:32 +0800 Message-ID: Subject: Re: [PATCH v1 2/3] dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path To: AngeloGioacchino Del Regno Cc: chunkuang.hu@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, shawn.sung@mediatek.com, yu-chang.lee@mediatek.com, ck.hu@mediatek.com, jitao.shi@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Apr 8, 2024 at 6:16=E2=80=AFPM AngeloGioacchino Del Regno wrote: > > Il 08/04/24 05:20, Chen-Yu Tsai ha scritto: > > On Thu, Apr 4, 2024 at 4:16=E2=80=AFPM AngeloGioacchino Del Regno > > wrote: > >> > >> Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths > >> per HW instance (so potentially up to six displays for multi-vdo SoCs)= . > >> > >> The MMSYS or VDOSYS is always the first component in the DDP pipeline, > >> so it only supports an output port with multiple endpoints - where eac= h > >> endpoint defines the starting point for one of the (currently three) > >> possible hardware paths. > >> > >> Signed-off-by: AngeloGioacchino Del Regno > >> --- > >> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 23 +++++++++++++++++= ++ > >> 1 file changed, 23 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,m= msys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y= aml > >> index b3c6888c1457..90758bb5bcb1 100644 > >> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya= ml > >> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya= ml > >> @@ -93,6 +93,29 @@ properties: > >> '#reset-cells': > >> const: 1 > >> > >> + port: > >> + $ref: /schemas/graph.yaml#/properties/port > >> + description: > >> + Output port node. This port connects the MMSYS/VDOSYS output to > >> + the first component of one display pipeline, for example one of > >> + the available OVL or RDMA blocks. > >> + Some MediaTek SoCs support up to three display outputs per MMSY= S. > >> + properties: > >> + endpoint@0: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the primary display pipeline > >> + > >> + endpoint@1: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the secondary display pipeline > >> + > >> + endpoint@2: > >> + $ref: /schemas/graph.yaml#/properties/endpoint > >> + description: Output to the tertiary display pipeline > >> + > >> + required: > >> + - endpoint@0 > >> + > > > > Technically the mmsys device serves as an glue layer for the display > > pipeline, providing things like clock control and signal routing; the > > device itself is not part of the pipeline, and probably shouldn't be > > part of the graph? > > > > That is (only) partially true: in the case of older SoCs, the MMSYS can o= nly > connect to a single first IP of the pipeline, but in the case of newer on= es, > and especially (but not limited to) MT8195 onwards having multiple instan= ces > of VDOSYS, that really becomes part of the pipeline. > > This is not because of the possible different first IP in the pipeline, b= ut > because of support for dual-interface (DSI and DP) that, in even newer So= Cs, > can be done with cross-mmsys (cross-vdosys, actually...) as some of those= do > have the two in different VDOs. > > So yes, this can be done without the graph in MMSYS *in this precise mome= nt in > time*, but we'll anyway end up adding it sooner than later - and I'm doin= g this > right now, instead of later, because it's also simplifying the implementa= tion > so like that I'm "catching two birds with one stone" :-) I see. Thanks for sorting it out. We had something similar on Allwinner platforms but it was never as complex or flexible as this. ChenYu > Cheers, > Angelo > > > ChenYu > > > >> required: > >> - compatible > >> - reg > >> -- > >> 2.44.0 > >> > >