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Message-ID: <3df74a0a-6778-43c4-a8c2-70d71c324f6a@arm.com>
Date: Tue, 9 Apr 2024 14:33:18 +0100
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Subject: Re: [PATCH] perf vendor events arm64: AmpereOne/AmpereOneX: Mark
 L1D_CACHE_INVAL impacted by errata
To: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Cc: Will Deacon <will@kernel.org>, Peter Zijlstra <peterz@infradead.org>,
 Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>,
 Alexander Shishkin <alexander.shishkin@linux.intel.com>,
 Jiri Olsa <jolsa@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>,
 linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org,
 linux-kernel@vger.kernel.org, John Garry <john.g.garry@oracle.com>,
 Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linux.dev>,
 Arnaldo Carvalho de Melo <acme@kernel.org>,
 Namhyung Kim <namhyung@kernel.org>, Ian Rogers <irogers@google.com>
References: <20240408214022.541839-1-ilkka@os.amperecomputing.com>
Content-Language: en-US
From: James Clark <james.clark@arm.com>
In-Reply-To: <20240408214022.541839-1-ilkka@os.amperecomputing.com>
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On 08/04/2024 22:40, Ilkka Koskinen wrote:
> L1D_CACHE_INVAL overcounts in certain situations. See AC03_CPU_41 and
> AC04_CPU_1 for more details. Mark the event impacted by the errata.
> 
> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
> ---
>  tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json  | 4 +++-
>  tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json | 4 +++-
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
> index 7a2b7b200f14..ac75f12e27bf 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
> @@ -9,7 +9,9 @@
>          "ArchStdEvent": "L1D_CACHE_REFILL_RD"
>      },
>      {
> -        "ArchStdEvent": "L1D_CACHE_INVAL"
> +        "ArchStdEvent": "L1D_CACHE_INVAL",
> +        "Errata": "Errata AC03_CPU_41",
> +        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
>      },
>      {
>          "ArchStdEvent": "L1D_TLB_REFILL_RD"
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
> index c50d8e930b05..f4bfe7083a6b 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/cache.json
> @@ -9,7 +9,9 @@
>          "ArchStdEvent": "L1D_CACHE_REFILL_RD"
>      },
>      {
> -        "ArchStdEvent": "L1D_CACHE_INVAL"
> +        "ArchStdEvent": "L1D_CACHE_INVAL",
> +        "Errata": "Errata AC04_CPU_1",
> +        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
>      },
>      {
>          "ArchStdEvent": "L1D_TLB_REFILL_RD"

Reviewed-by: James Clark <james.clark@arm.com>