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AJvYcCVB6vjnfYPcNNnuYZmeMNK/fTXlvu61gDLKAwHCzmTagDtlwqnOYcTPiHA11eQ8dGc+frHhcwaq2EDxB6KNnhXEK6QVHTXPCP/XKcEc X-Gm-Message-State: AOJu0YyZ56kqZ8kkUSHs0AhYfay8Cibivtnv27D53OCb/RvT4K8kLitF BoKNaaiPJEARcQ3SKJLmvnBfBLAGfGz1NRSQNVNQGMP6OTv3QOiu2QVZkjee8Z8FnwSveUCXPgD hxY117YaWhVouJkmQ9IH3hUMnFM4= X-Received: by 2002:a05:651c:1050:b0:2d8:606d:c797 with SMTP id x16-20020a05651c105000b002d8606dc797mr58893ljm.10.1712680784496; Tue, 09 Apr 2024 09:39:44 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240409100503.274629-1-ubizjak@gmail.com> <20240409100503.274629-3-ubizjak@gmail.com> In-Reply-To: From: Uros Bizjak Date: Tue, 9 Apr 2024 18:39:32 +0200 Message-ID: Subject: Re: [PATCH 2/6] locking/atomic/x86: Rewrite x86_32 arch_atomic64_{,fetch}_{and,or,xor}() functions To: Mark Rutland Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Peter Zijlstra Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Apr 9, 2024 at 6:34=E2=80=AFPM Mark Rutland = wrote: > > > > ... and then use that in each of the instances below. > > > > > > > > That way the subtlety is clearly documented, and it'd more clearly = align with > > > > the x86_64 verions. > > > > > > This is an excellent idea. The separate definitions needs to be place= d > > > in atomic64_32.h and atomic_64_64.h (due to use of atomic64_t > > > typedef), but it will allow the same unification of functions between > > > x64_32 and x64_64 as the approach with __READ_ONCE(). > > > > Something like this: > > > > --cut here-- > > /* > > * This function is intended to preload the value from atomic64_t > > * location in a non-atomic way. The read might be torn, but can > > * safely be consumed by the compare-and-swap loop. > > */ > > static __always_inline s64 arch_atomic64_read_tearable(atomic64_t *v) > > { > > /* > > * See the comment in arch_atomic_read() on why we use > > * __READ_ONCE() instead of READ_ONCE_NOCHECK() here. > > */ > > return __READ_ONCE(v->counter); > > } > > --cut here-- > > > > Thanks, > > Uros. > > Yeah, something of that shape. > > Having thought for a bit longer, it's probably better to use '_torn' rath= er > than '_tearable' (i.e. name this arch_atomic64_read_torn()). > > It'd be nice if we could specify the usage restrictions a bit more clearl= y, > since this can only be used for compare-and-swap loops that implement > unconditional atomics. (e.g. arch_atomic64_and(), but not > arch_atomic_add_unless()). > > So I'd suggest: Eh, just sent a v2 a second before I received your mail. I'll respin the patchset tomorrow to include your suggested text. Please note that v2 patch set avoids all cosmetic changes. Thanks, Uros. > > /* > * Read an atomic64_t non-atomically. > * > * This is intended to be used in cases where a subsequent atomic operati= on > * will handle the torn value, and can be used to prime the first iterati= on of > * unconditional try_cmpxchg() loops, e.g. > * > * s64 val =3D arch_atomic64_read_torn(v); > * do { } while (!arch_atomic_try_cmpxchg(v, &val, val OP i); > * > * This is NOT safe to use where the value is not always checked by a > * subsequent atomic operation, such as in conditional try_cmpxchg() loop= s that > * can break before the atomic, e.g. > * > * s64 val =3D arch_atomic64_read_torn(v); > * do { > * if (condition(val)) > * break; > * } while (!arch_atomic_try_cmpxchg(v, &val, val OP i); > */ > static __always_inline s64 arch_atomic64_read_torn(atomic64_t *v) > { > /* See comment in arch_atomic_read() */ > return __READ_ONCE(v->counter); > } > > Mark.