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AJvYcCU7M8YWXwWFKrh51UslQ9vknFQfM9g7L1L4Rj55bQGzd7YB9A1HaCT2jXuHG6lI7ELJomB8AoLAJukZNi0nSHXUMj6Lf1aYBzi/HHY2 X-Gm-Message-State: AOJu0YyHRmbIi+yYwSyjIUOhfWbjsRLb7DF4g8ExRpjol2+7ja3Q0dvY OiqoL7FhA3L7sDZCZisJTDQCBakaP3Yg3tn9FOo1S1E/c5OhE/VqLT8e0Hm888e1hT9IR8PPX+9 6R1HSSA7NYFibxY1qslKRfzLvdcI3Ywx9OiyrmQ== X-Received: by 2002:a25:8403:0:b0:dcc:fea7:7f7b with SMTP id u3-20020a258403000000b00dccfea77f7bmr631031ybk.11.1712687482548; Tue, 09 Apr 2024 11:31:22 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> <20240405-topic-smem_speedbin-v1-3-ce2b864251b1@linaro.org> <74ebd488-15c1-47a5-86f4-14263e3a914e@linaro.org> In-Reply-To: <74ebd488-15c1-47a5-86f4-14263e3a914e@linaro.org> From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 21:31:11 +0300 Message-ID: Subject: Re: [PATCH 3/6] drm/msm/adreno: Allow specifying default speedbin value To: Konrad Dybcio Cc: Rob Clark , Bjorn Andersson , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 9 Apr 2024 at 21:27, Konrad Dybcio wrote= : > > > > On 4/9/24 20:15, Dmitry Baryshkov wrote: > > On Tue, Apr 09, 2024 at 08:07:56PM +0200, Konrad Dybcio wrote: > >> > >> > >> On 4/9/24 20:04, Dmitry Baryshkov wrote: > >>> On Tue, Apr 09, 2024 at 10:12:00AM -0700, Rob Clark wrote: > >>>> On Tue, Apr 9, 2024 at 8:23=E2=80=AFAM Dmitry Baryshkov > >>>> wrote: > >>>>> > >>>>> On Tue, Apr 09, 2024 at 05:12:46PM +0200, Konrad Dybcio wrote: > >>>>>> > >>>>>> > >>>>>> On 4/6/24 04:56, Dmitry Baryshkov wrote: > >>>>>>> On Fri, Apr 05, 2024 at 10:41:31AM +0200, Konrad Dybcio wrote: > >>>>>>>> From: Neil Armstrong > >>>>>>>> > >>>>>>>> Usually, speedbin 0 is the "super SKU", a.k.a the one which can = clock > >>>>>>>> the highest. Falling back to it when things go wrong is largely > >>>>>>>> suboptimal, as more often than not, the top frequencies are not > >>>>>>>> supposed to work on other bins. > >>>>>>> > >>>>>>> Isn't it better to just return an error here instead of trying to= guess > >>>>>>> which speedbin to use? > >>>>>> > >>>>>> Not sure. I'd rather better compatibility for e.g. booting up a ne= w > >>>>>> laptop with just dt. > >>>>> > >>>>> New speedbin can have lower max speed, so by attempting to run it a= t > >>>>> higher freq you might be breaking it. > >>>> > >>>> Usually there are some OPPs in common to all speedbins, so picking a > >>>> freq from that set would seem like the safe thing to do > >>> > >>> Well, the issue is about an uknown speed bin. So in theory we know > >>> nothing about the set of speeds itsupports. My point is that we shoul= d > >>> simplfy fail in such case. > >> > >> Or we could allow e.g. the lowest frequency (or 2) which if often shar= ed > >> across the board to work, giving a compromise between OOBE and sanity > > > > That's also an option. But we should not be using existing speed table = for > > the unknown bin. > > I derived this logic from msm-5.15 where it's "intended behavior".. I > suppose we can do better as you said though > > There have been cases in the past where the default speed bin ended up > having a higher max freq than subsequent ones, and I don't think I can > trust this product/feature code approach to guarantee this never > happening again. > > So. I think sticking to a single lowest freq and printing a big red line > in dmesg makes sense here Make 0x80 the default supported-hw, make sure that the lowest freq has 0xff. Plus big-red-line. And hope that we'll never see 16 speed bins for the hardware. --=20 With best wishes Dmitry