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X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QbhKim65hE7XxkqOXjhfKMYpi7q0OsP0l+pU5OeZ8MDch76HwNzMFb7ETK2K+Q937yeiR4Yv3AHhJolmap7h9qQHnO6SiobYtp4s1QJ4lO8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR10MB4927 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-09_12,2024-04-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 malwarescore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404100009 X-Proofpoint-GUID: aNR12FLWspkRq_ClfwAVYn4kgeoInLLh X-Proofpoint-ORIG-GUID: aNR12FLWspkRq_ClfwAVYn4kgeoInLLh On 4/9/24 02:45, Chao Gao wrote: >> diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c >> index 4b74ea91f4e6..853cafe4a9af 100644 >> --- a/arch/x86/kvm/svm/avic.c >> +++ b/arch/x86/kvm/svm/avic.c >> @@ -165,8 +165,10 @@ int avic_ga_log_notifier(u32 ga_tag) >> * bit in the vAPIC backing page. So, we just need to schedule >> * in the vcpu. >> */ >> - if (vcpu) >> + if (vcpu) { >> kvm_vcpu_wake_up(vcpu); >> + ++vcpu->stat.ga_log_event; >> + } >> > > I am not sure why this is added for SVM only. I am mostly familiar with AVIC, and much less so with VMX's PI, so this is why I am likely missing potential stats that could be useful to expose from the VMX side. I'll be glad to implement any other suggestions you have. it looks to me GALog events are > similar to Intel IOMMU's wakeup events. Can we have a general name? maybe > iommu_wakeup_event I believe that after: d588bb9be1da ("KVM: VMX: enable IPI virtualization") both the VT-d PI and the virtualized IPIs code paths will use POSTED_INTR_WAKEUP_VECTOR for interrupts targeting a blocked vCPU. So on Intel hosts enabling IPI virtualization, a counter incremented in pi_wakeup_handler() would record interrupts from both virtualized IPIs and VT-d sources. I don't think it is correct to generalize this counter since AMD's implementation is different; when a blocked vCPU is targeted: - by device interrupts, it uses the GA Log mechanism - by an IPI, it generates an AVIC_INCOMPLETE_IPI #VMEXIT If the reasoning above is correct, we can add a VMX specific counter (vmx_pi_wakeup_event?) that is increased in pi_wakeup_handler() as you suggest, and document the difference in behavior so that is not confused as equivalent with the ga_log_event counter. An alternative if we'd like to have a common 'iommu_wakeup_event' is to add filtering on pi_wakeup_handler() and only increment the common counter if IPI virtualization is not enabled (i.e. !vmx_can_use_ipiv()), in which case we'd only handle device interrupts and it becomes the parallel case to GA Log events. That leaves us with a VMX-specific counter (vmx_pi_wakeup_event) which provides no definition between interrupt sources when IPI virtualization is enabled, or when disabled we have a common/generic counter (iommu_wakeup_event) that applies to both vendors. Please let me know if you agree with this approach or have other suggestions. Thank you, Alejandro > > and increase the counter after the kvm_vcpu_wake_up() call in pi_wakeup_handler().