Received-SPF: pass (google.com: domain of linux-kernel+bounces-138202-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Date: Wed, 10 Apr 2024 09:50:20 +0100
Message-ID: <86v84psisz.wl-maz@kernel.org>
From: Marc Zyngier <maz@kernel.org>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Gavin Shan <gshan@redhat.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	catalin.marinas@arm.com,
	will@kernel.org,
	akpm@linux-foundation.org,
	oliver.upton@linux.dev,
	apopple@nvidia.com,
	rananta@google.com,
	mark.rutland@arm.com,
	v-songbaohua@oppo.com,
	yangyicong@hisilicon.com,
	shahuang@redhat.com,
	yihyu@redhat.com,
	shan.gavin@gmail.com
Subject: Re: [PATCH v3 3/3] arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGES
In-Reply-To: <27718d41-32cb-4976-b50e-e9237da7aedf@arm.com>
References: <20240405035852.1532010-1-gshan@redhat.com>
	<20240405035852.1532010-4-gshan@redhat.com>
	<27718d41-32cb-4976-b50e-e9237da7aedf@arm.com>
User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue)
 FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2
 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO)
Precedence: bulk
MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue")
Content-Type: text/plain; charset=US-ASCII

On Mon, 08 Apr 2024 09:43:44 +0100,
Ryan Roberts <ryan.roberts@arm.com> wrote:
> 
> On 05/04/2024 04:58, Gavin Shan wrote:
> > MAX_TLBI_RANGE_PAGES pages is covered by SCALE#3 and NUM#31 and it's
> > supported now. Allow TLBI RANGE operation when the number of pages is
> > equal to MAX_TLBI_RANGE_PAGES in __flush_tlb_range_nosync().
> > 
> > Suggested-by: Marc Zyngier <maz@kernel.org>
> > Signed-off-by: Gavin Shan <gshan@redhat.com>
> 
> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com>
> 
> > ---
> >  arch/arm64/include/asm/tlbflush.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> > index 243d71f7bc1f..95fbc8c05607 100644
> > --- a/arch/arm64/include/asm/tlbflush.h
> > +++ b/arch/arm64/include/asm/tlbflush.h
> > @@ -446,11 +446,11 @@ static inline void __flush_tlb_range_nosync(struct vm_area_struct *vma,
> >  	 * When not uses TLB range ops, we can handle up to
> >  	 * (MAX_DVM_OPS - 1) pages;
> >  	 * When uses TLB range ops, we can handle up to
> > -	 * (MAX_TLBI_RANGE_PAGES - 1) pages.
> > +	 * MAX_TLBI_RANGE_PAGES pages.
> >  	 */
> >  	if ((!system_supports_tlb_range() &&
> >  	     (end - start) >= (MAX_DVM_OPS * stride)) ||
> > -	    pages >= MAX_TLBI_RANGE_PAGES) {
> > +	    pages > MAX_TLBI_RANGE_PAGES) {
> 
> As a further enhancement, I wonder if it might be better to test:
> 
> 	pages * 4 / MAX_TLBI_RANGE_PAGES > MAX_DVM_OPS
> 
> Then add an extra loop over __flush_tlb_range_op(), like KVM does.
> 
> The math is trying to express that there are a maximum of 4 tlbi range
> instructions for MAX_TLBI_RANGE_PAGES pages (1 per scale) and we only need to
> fall back to flushing the whole mm if it could generate more than MAX_DVM_OPS ops.

That'd be a good enhancement indeed, although I wonder if that occurs
as often as we see it on the KVM side. But in any case, adding
consistency amongst the users of __flush_tlb_range_op() can only be
beneficial.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.