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Date: Wed, 10 Apr 2024 12:55:35 -0300
From: Jason Gunthorpe <jgg@ziepe.ca>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Kevin Tian <kevin.tian@intel.com>,
	Tina Zhang <tina.zhang@intel.com>, Yi Liu <yi.l.liu@intel.com>,
	iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 09/12] iommu/vt-d: Use cache helpers in
 arch_invalidate_secondary_tlbs
Message-ID: <20240410155535.GI223006@ziepe.ca>
References: <20240410020844.253535-1-baolu.lu@linux.intel.com>
 <20240410020844.253535-10-baolu.lu@linux.intel.com>
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In-Reply-To: <20240410020844.253535-10-baolu.lu@linux.intel.com>

On Wed, Apr 10, 2024 at 10:08:41AM +0800, Lu Baolu wrote:
>  /* Pages have been freed at this point */
>  static void intel_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn,
>  					struct mm_struct *mm,
>  					unsigned long start, unsigned long end)
>  {
>  	struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
> +	struct dmar_domain *domain = svm->domain;
>  
>  	if (start == 0 && end == -1UL) {

ULONG_MAX ideally.

> -		intel_flush_svm_all(svm);
> +		cache_tag_flush_all(domain);
>  		return;
>  	}
>  
> -	intel_flush_svm_range(svm, start,
> -			      (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0);
> +	cache_tag_flush_range(domain, start, end, 0);

Be mindful of the note from the ARM driver:

        /*
         * The mm_types defines vm_end as the first byte after the end address,
         * different from IOMMU subsystem using the last address of an address
         * range. So do a simple translation here by calculating size correctly.
         */
        size = end - start;

Given that the cache_tag_flush_range's are all tied directly to the
iommu gather API, this is probably missing a -1 though perhaps it does
not cause a functional problem here.

Jason