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Date: Wed, 10 Apr 2024 22:43:10 +0200
From: Stephan Gerhold <stephan@gerhold.net>
To: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] arm64: dts: qcom: sa8155p-adp: use correct gpio for
 SDHC2 CD
Message-ID: <Zhb53i8-pJhDMVZM@gerhold.net>
References: <20240410134022.732767-1-volodymyr_babchuk@epam.com>
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On Wed, Apr 10, 2024 at 01:41:30PM +0000, Volodymyr Babchuk wrote:
> Card Detect pin for SHDC2 on SA8155P-ADP is connected to GPIO4 of
> PMM8155AU_1, not to internal TLMM. This change fixes two issues at
> once: not working ethernet (because GPIO4 is used for MAC TX) and SD
> detection.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> index 5e4287f8c8cd1..6b08ce246b78c 100644
> --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> @@ -384,7 +384,7 @@ &remoteproc_cdsp {
>  &sdhc_2 {
>  	status = "okay";
>  
> -	cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
> +	cd-gpios = <&pmm8155au_1_gpios 4 GPIO_ACTIVE_LOW>;

Good catch!

>  	pinctrl-names = "default", "sleep";
>  	pinctrl-0 = <&sdc2_on>;
>  	pinctrl-1 = <&sdc2_off>;

These two pinctrl configure "gpio96" for "sd-cd-pins". Yet another wrong
GPIO? Should probably drop that and add proper pinctrl for the actual
GPIO in the PMIC. Seems like Qualcomm configured the PMIC GPIO with
pull-up downstream [1] (not sure if this is the right file). It might be
redundant if there is an external pull-up on the board, but only the
schematic could tell that for sure.

FWIW: Looking closer at the broken commit, the regulator voltage setup
of &sdhc_2 looks suspicious too. Typically one would want a 1.8V capable
regulator for the vqmmc-supply to properly use ultra high-speed modes,
but &vreg_l13c_2p96 seems to be configured with 2.504V-2.960V at the
moment. On downstream it seems to be 1.8V-2.96V [2] (again, not sure if
this is the right file). I would recommend re-checking this too and
testing if UHS cards are detected correctly (if you have the board).

&vreg_l17a_2p96 has the same 2.504V-2.960V, but has 2.704V-2.960V
downstream [3]. This is close at least, might be fine as-is (but I'm not
convinced there is a good reason to differ there).

Thanks,
Stephan

[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/484af352989c912db8f3b6393fc090006029066f/arch/arm64/boot/dts/qcom/sa8155-pmic-overlay.dtsi#L206-214
[2]: https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/484af352989c912db8f3b6393fc090006029066f/arch/arm64/boot/dts/qcom/sa8155-regulator.dtsi#L635-642
[3]: https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/484af352989c912db8f3b6393fc090006029066f/arch/arm64/boot/dts/qcom/sa8155-regulator.dtsi#L363-370