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Date: Tue, 9 Apr 2024 17:12:04 +0100
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com>
CC: "Huang, Ying" <ying.huang@intel.com>, Gregory Price
	<gourry.memverge@gmail.com>, <aneesh.kumar@linux.ibm.com>, <mhocko@suse.com>,
	<tj@kernel.org>, <john@jagalactic.com>, Eishan Mirakhur
	<emirakhur@micron.com>, Vinicius Tavares Petrucci <vtavarespetr@micron.com>,
	Ravis OpenSrc <Ravis.OpenSrc@micron.com>, Alistair Popple
	<apopple@nvidia.com>, Srinivasulu Thanneeru <sthanneeru@micron.com>, SeongJae
 Park <sj@kernel.org>, Dan Williams <dan.j.williams@intel.com>, Vishal Verma
	<vishal.l.verma@intel.com>, Dave Jiang <dave.jiang@intel.com>, "Andrew
 Morton" <akpm@linux-foundation.org>, <nvdimm@lists.linux.dev>,
	<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>, "Linux Memory
 Management List" <linux-mm@kvack.org>, "Ho-Ren (Jack) Chuang"
	<horenc@vt.edu>, "Ho-Ren (Jack) Chuang" <horenchuang@gmail.com>,
	<qemu-devel@nongnu.org>, Hao Xiang <hao.xiang@bytedance.com>
Subject: Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after
 obtaining HMAT info
Message-ID: <20240409171204.00001710@Huawei.com>
In-Reply-To: <CAKPbEqpGM_nR+LKbsoFTviBZaKUKYqJ3zbJp9EOCJAGvuPy6aQ@mail.gmail.com>
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	<20240405000707.2670063-3-horenchuang@bytedance.com>
	<20240405150244.00004b49@Huawei.com>
	<CAKPbEqpGM_nR+LKbsoFTviBZaKUKYqJ3zbJp9EOCJAGvuPy6aQ@mail.gmail.com>
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On Fri, 5 Apr 2024 15:43:47 -0700
"Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com> wrote:

> On Fri, Apr 5, 2024 at 7:03=E2=80=AFAM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Fri,  5 Apr 2024 00:07:06 +0000
> > "Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com> wrote:
> > =20
> > > The current implementation treats emulated memory devices, such as
> > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal =
memory
> > > (E820_TYPE_RAM). However, these emulated devices have different
> > > characteristics than traditional DRAM, making it important to
> > > distinguish them. Thus, we modify the tiered memory initialization pr=
ocess
> > > to introduce a delay specifically for CPUless NUMA nodes. This delay
> > > ensures that the memory tier initialization for these nodes is deferr=
ed
> > > until HMAT information is obtained during the boot process. Finally,
> > > demotion tables are recalculated at the end.
> > >
> > > * late_initcall(memory_tier_late_init);
> > > Some device drivers may have initialized memory tiers between
> > > `memory_tier_init()` and `memory_tier_late_init()`, potentially bring=
ing
> > > online memory nodes and configuring memory tiers. They should be excl=
uded
> > > in the late init.
> > >
> > > * Handle cases where there is no HMAT when creating memory tiers
> > > There is a scenario where a CPUless node does not provide HMAT inform=
ation.
> > > If no HMAT is specified, it falls back to using the default DRAM tier.
> > >
> > > * Introduce another new lock `default_dram_perf_lock` for adist calcu=
lation
> > > In the current implementation, iterating through CPUlist nodes requir=
es
> > > holding the `memory_tier_lock`. However, `mt_calc_adistance()` will e=
nd up
> > > trying to acquire the same lock, leading to a potential deadlock.
> > > Therefore, we propose introducing a standalone `default_dram_perf_loc=
k` to
> > > protect `default_dram_perf_*`. This approach not only avoids deadlock
> > > but also prevents holding a large lock simultaneously.
> > >
> > > * Upgrade `set_node_memory_tier` to support additional cases, includi=
ng
> > >   default DRAM, late CPUless, and hot-plugged initializations.
> > > To cover hot-plugged memory nodes, `mt_calc_adistance()` and
> > > `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()`=
 to
> > > handle cases where memtype is not initialized and where HMAT informat=
ion is
> > > available.
> > >
> > > * Introduce `default_memory_types` for those memory types that are not
> > >   initialized by device drivers.
> > > Because late initialized memory and default DRAM memory need to be ma=
naged,
> > > a default memory type is created for storing all memory types that are
> > > not initialized by device drivers and as a fallback.
> > >
> > > Signed-off-by: Ho-Ren (Jack) Chuang <horenchuang@bytedance.com>
> > > Signed-off-by: Hao Xiang <hao.xiang@bytedance.com>
> > > Reviewed-by: "Huang, Ying" <ying.huang@intel.com> =20
> >
> > Hi - one remaining question. Why can't we delay init for all nodes
> > to either drivers or your fallback late_initcall code.
> > It would be nice to reduce possible code paths. =20
>=20
> I try not to change too much of the existing code structure in
> this patchset.
>=20
> To me, postponing/moving all memory tier registrations to
> late_initcall() is another possible action item for the next patchset.
>=20
> After tier_mem(), hmat_init() is called, which requires registering
> `default_dram_type` info. This is when `default_dram_type` is needed.
> However, it is indeed possible to postpone the latter part,
> set_node_memory_tier(), to `late_init(). So, memory_tier_init() can
> indeed be split into two parts, and the latter part can be moved to
> late_initcall() to be processed together.
>=20
> Doing this all memory-type drivers have to call late_initcall() to
> register a memory tier. I=E2=80=99m not sure how many they are?
>=20
> What do you guys think?

Gut feeling - if you are going to move it for some cases, move it for
all of them.  Then we only have to test once ;)

J
>=20
> >
> > Jonathan
> >
> > =20
> > > ---
> > >  mm/memory-tiers.c | 94 +++++++++++++++++++++++++++++++++++----------=
--
> > >  1 file changed, 70 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c
> > > index 516b144fd45a..6632102bd5c9 100644
> > > --- a/mm/memory-tiers.c
> > > +++ b/mm/memory-tiers.c =20
> >
> >
> > =20
> > > @@ -855,7 +892,8 @@ static int __init memory_tier_init(void)
> > >        * For now we can have 4 faster memory tiers with smaller adist=
ance
> > >        * than default DRAM tier.
> > >        */
> > > -     default_dram_type =3D alloc_memory_type(MEMTIER_ADISTANCE_DRAM);
> > > +     default_dram_type =3D mt_find_alloc_memory_type(MEMTIER_ADISTAN=
CE_DRAM,
> > > +                                                   &default_memory_t=
ypes);
> > >       if (IS_ERR(default_dram_type))
> > >               panic("%s() failed to allocate default DRAM tier\n", __=
func__);
> > >
> > > @@ -865,6 +903,14 @@ static int __init memory_tier_init(void)
> > >        * types assigned.
> > >        */
> > >       for_each_node_state(node, N_MEMORY) {
> > > +             if (!node_state(node, N_CPU))
> > > +                     /*
> > > +                      * Defer memory tier initialization on
> > > +                      * CPUless numa nodes. These will be initialized
> > > +                      * after firmware and devices are initialized. =
=20
> >
> > Could the comment also say why we can't defer them all?
> >
> > (In an odd coincidence we have a similar issue for some CPU hotplug
> >  related bring up where review feedback was move all cases later).
> > =20
> > > +                      */
> > > +                     continue;
> > > +
> > >               memtier =3D set_node_memory_tier(node);
> > >               if (IS_ERR(memtier))
> > >                       /* =20
> > =20
>=20
>=20