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[209.85.218.44]) by smtp.gmail.com with ESMTPSA id dd15-20020a056402312f00b005689bfe2688sm208271edb.39.2024.04.10.18.38.44 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Apr 2024 18:38:44 -0700 (PDT) Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a44ad785a44so849182366b.3 for ; Wed, 10 Apr 2024 18:38:44 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUDaalCiw2UemOpZyCojOBkv7qzNd+VF0EqbUAgdXkJc7Zz6s8+xSF59KTV8oZcax5yl3n1xNjm/JCu6x7BV8ooqea1wL7OD6/96INw X-Received: by 2002:a17:906:cb8a:b0:a51:d7c8:300c with SMTP id mf10-20020a170906cb8a00b00a51d7c8300cmr2914356ejb.17.1712799503901; Wed, 10 Apr 2024 18:38:23 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240411-tso-v1-0-754f11abfbff@marcan.st> In-Reply-To: <20240411-tso-v1-0-754f11abfbff@marcan.st> From: Neal Gompa Date: Wed, 10 Apr 2024 21:37:47 -0400 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 0/4] arm64: Support the TSO memory model To: Hector Martin Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland , Zayd Qumsieh , Justin Lu , Ryan Houdek , Mark Brown , Ard Biesheuvel , Mateusz Guzik , Anshuman Khandual , Oliver Upton , Miguel Luis , Joey Gouly , Christoph Paasch , Kees Cook , Sami Tolvanen , Baoquan He , Joel Granados , Dawei Li , Andrew Morton , Florent Revest , David Hildenbrand , Stefan Roesch , Andy Chiu , Josh Triplett , Oleg Nesterov , Helge Deller , Zev Weiss , Ondrej Mosnacek , Miguel Ojeda , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Asahi Linux Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Apr 10, 2024 at 8:51=E2=80=AFPM Hector Martin wr= ote: > > x86 CPUs implement a stricter memory modern than ARM64 (TSO). For this > reason, x86 emulation on baseline ARM64 systems requires very expensive > memory model emulation. Having hardware that supports this natively is > therefore very attractive. Such hardware, in fact, exists. This series > adds support for userspace to identify when TSO is available and > toggle it on, if supported. > > Some ARM64 CPUs intrinsically implement the TSO memory model, while > others expose is as an IMPDEF control. Apple Silicon SoCs are in the > latter category. Using TSO for x86 emulation on chips that support it > has been shown to provide a massive performance boost [1]. > > Patch 1 introduces the PR_{SET,GET}_MEM_MODEL userspace control, which > is initially not implemented for any architectures. > > Patch 2 implements it for CPUs which are known, to the best of my > knowledge, to always implement the TSO memory model unconditionally. > This uses the cpufeature mechanism to only enable this if *all* cores in > the system meet the requirements. > > Patch 3 adds the scaffolding necesasry to save/restore the ACTLR_EL1 > register across context switches. This register contains IMPDEF flags > related to CPU execution, and on Apple CPUs this is where the runtime > TSO toggle bit is implemented. Other CPUs could conceivably benefit from > this scaffolding if they also use ACTLR_EL1 for things that could > ostensibly be runtime controlled and context-switched. For this to work, > ACTLR_EL1 must have a uniform layout across all cores in the system. > > Finally, patch 4 implements PR_{SET,GET}_MEM_MODEL for Apple CPUs by > hooking it up to flip the appropriate ACTLR_EL1 bit when the Apple TSO > feature is detected (on all CPUs, which also implies the uniform > ACTLR_EL1 layout). > > This series has been brewing in the downstream Asahi Linux tree for a > while now, and ships to thousands of users. A subset have been using it > with FEX-Emu, which already supports this feature. This rebase on > v6.9-rc1 is only build-tested (all intermediate commits with and without > the config enabled, on ARM64) but I'll update the downstream branch soon > with this version and get it pushed out to users/testers. > > The Apple support works on bare metal and *should* work exactly the same > way on macOS VMs (as alluded to by Zayd in his independent submission [3]= ), > though I haven't personally verified this. KVM support for this is left > for a future patchset. > > (Apologies for the large Cc: list; I want to make sure nobody who got > Cced on Zayd's alternate take is left out of this one.) > > [1] https://fex-emu.com/FEX-2306/ > [2] https://github.com/AsahiLinux/linux/tree/bits/220-tso > [3] https://lore.kernel.org/lkml/20240410211652.16640-1-zayd_qumsieh@appl= e.com/ > > To: Catalin Marinas > To: Will Deacon > To: Marc Zyngier > To: Mark Rutland > Cc: Zayd Qumsieh > Cc: Justin Lu > Cc: Ryan Houdek > Cc: Mark Brown > Cc: Ard Biesheuvel > Cc: Mateusz Guzik > Cc: Anshuman Khandual > Cc: Oliver Upton > Cc: Miguel Luis > Cc: Joey Gouly > Cc: Christoph Paasch > Cc: Kees Cook > Cc: Sami Tolvanen > Cc: Baoquan He > Cc: Joel Granados > Cc: Dawei Li > Cc: Andrew Morton > Cc: Florent Revest > Cc: David Hildenbrand > Cc: Stefan Roesch > Cc: Andy Chiu > Cc: Josh Triplett > Cc: Oleg Nesterov > Cc: Helge Deller > Cc: Zev Weiss > Cc: Ondrej Mosnacek > Cc: Miguel Ojeda > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: Asahi Linux > > Signed-off-by: Hector Martin > --- > Hector Martin (4): > prctl: Introduce PR_{SET,GET}_MEM_MODEL > arm64: Implement PR_{GET,SET}_MEM_MODEL for always-TSO CPUs > arm64: Introduce scaffolding to add ACTLR_EL1 to thread state > arm64: Implement Apple IMPDEF TSO memory model control > > arch/arm64/Kconfig | 14 ++++++ > arch/arm64/include/asm/apple_cpufeature.h | 15 +++++++ > arch/arm64/include/asm/cpufeature.h | 10 +++++ > arch/arm64/include/asm/processor.h | 3 ++ > arch/arm64/kernel/Makefile | 3 +- > arch/arm64/kernel/cpufeature.c | 11 ++--- > arch/arm64/kernel/cpufeature_impdef.c | 61 +++++++++++++++++++++++++= + > arch/arm64/kernel/process.c | 71 +++++++++++++++++++++++++= ++++++ > arch/arm64/kernel/setup.c | 8 ++++ > arch/arm64/tools/cpucaps | 2 + > include/linux/memory_ordering_model.h | 11 +++++ > include/uapi/linux/prctl.h | 5 +++ > kernel/sys.c | 21 +++++++++ > 13 files changed, 229 insertions(+), 6 deletions(-) > --- > base-commit: 4cece764965020c22cff7665b18a012006359095 > change-id: 20240411-tso-e86fdceb94b8 > The series looks good to me. Reviewed-by: Neal Gompa --=20 =E7=9C=9F=E5=AE=9F=E3=81=AF=E3=81=84=E3=81=A4=E3=82=82=E4=B8=80=E3=81=A4=EF= =BC=81/ Always, there's only one truth!