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Thu, 11 Apr 2024 06:58:25 GMT Received: from [10.253.12.44] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 10 Apr 2024 23:58:20 -0700 Message-ID: <229fb5b2-34c9-402b-9812-f91e6cc31c57@quicinc.com> Date: Thu, 11 Apr 2024 14:58:18 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/3] input: pm8xxx-vibrator: add new SPMI vibrator support Content-Language: en-US To: Konrad Dybcio , , Andy Gross , Bjorn Andersson , Dmitry Torokhov , Rob Herring , "Krzysztof Kozlowski" , Dmitry Baryshkov CC: , , , References: <20240401-pm8xxx-vibrator-new-design-v8-0-6f2b8b03b4c7@quicinc.com> <20240401-pm8xxx-vibrator-new-design-v8-3-6f2b8b03b4c7@quicinc.com> <3f8c970c-6a0d-4fc3-a2d3-e0797e7055cf@linaro.org> From: Fenglin Wu In-Reply-To: <3f8c970c-6a0d-4fc3-a2d3-e0797e7055cf@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3rYAA5HCMwsUzQ4-R7R_mCoI_ADh6Or3 X-Proofpoint-GUID: 3rYAA5HCMwsUzQ4-R7R_mCoI_ADh6Or3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_02,2024-04-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 mlxlogscore=685 phishscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404110048 Hi Konrad, On 4/11/2024 2:10 AM, Konrad Dybcio wrote: > > >> +    if (regs->drv2_mask) { >> +        if (on) >> +            val = (vib->level << regs->drv2_shift) & regs->drv2_mask; >> +        else >> +            val = 0; >> +        rc = regmap_write(vib->regmap, vib->drv2_addr, val); > > Are you purposefuly zeroing out the other bits? > > If yes, consider regmap_write_bits here > If not, consider regmap_update_bits here > >> +        if (rc < 0) >> +            return rc; > > Ignore regmap_r/w errors, these mean a complete failure of the API and > we don't generally assume MMIO accesses can fail > > Unless SPMI is known to have issues here > Sorry, forgot to reply on this comment. Yes, SPMI transaction would fail (even with very low odds) on some boards if the layout of SPMI lines is not good enough. I'd like to keep the consistence since the whole driver also checks the regmap_r/w errors.