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Thu, 11 Apr 2024 00:02:29 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCW3ymnvmgL/wiph7Pgdv437f5qsEvbxTegxpqzFzo8GWRRrz+EQf2RbiD5cL9cMSH6ScCm1ayf3QIwPvzwDrOcUkqKBWwX95nSovyQ+ X-Gm-Message-State: AOJu0YyIaEhOHXixc6XY6OTVY8hMHgLJ6jw/CLgDbLJ3voZeu+qx76D7 6SlQ+2Iuf3wA/8+PK/T4oadxchwfNIEcZv9WB8eHOKq5LJftJcfuEAVUGNJRCchvy92qOBnCxdZ mb8ajF23H39O8m7y+yGC0u8C3Y9Y= X-Received: by 2002:a05:651c:102c:b0:2d6:fc0b:f122 with SMTP id w12-20020a05651c102c00b002d6fc0bf122mr2858466ljm.18.1712818947405; Thu, 11 Apr 2024 00:02:27 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240409164641.GC3219862@dev-arch.thelio-3990X> <20240410024126.21589-1-zhuqiuer1@huawei.com> <20240410024126.21589-2-zhuqiuer1@huawei.com> <20240410153526.GA3904754@dev-arch.thelio-3990X> In-Reply-To: <20240410153526.GA3904754@dev-arch.thelio-3990X> From: Ard Biesheuvel Date: Thu, 11 Apr 2024 09:02:15 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2] ARM: Add a memory clobber to the fmrx instruction To: Nathan Chancellor Cc: zhuqiuer , justinstitt@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, llvm@lists.linux.dev, morbo@google.com, ndesaulniers@google.com Content-Type: text/plain; charset="UTF-8" On Wed, 10 Apr 2024 at 17:35, Nathan Chancellor wrote: > > On Wed, Apr 10, 2024 at 02:31:11PM +0200, Ard Biesheuvel wrote: > > On Wed, 10 Apr 2024 at 04:41, zhuqiuer wrote: > > > > > > The instruction fmrx is used throughout the kernel, > > > where it is sometimes expected to be skipped > > > by incrementing the program counter, such as in vfpmodule.c:vfp_init(). > > > Therefore, the instruction should not be reordered when it is not intended. > > > Adding a barrier() instruction before and after this call cannot prevent > > > reordering by the compiler, as the fmrx instruction is constrained > > > by '=r', meaning it works on the general register but not on memory. > > > To ensure the order of the instruction after compiling, > > > adding a memory clobber is necessary. > > > > > > Below is the code snippet disassembled from the method: > > > vfpmodule.c:vfp_init(), compiled by LLVM. > > > > > > Before the patching: > > > xxxxx: xxxxx bl c010c688 > > > xxxxx: xxxxx mov r0, r4 > > > xxxxx: xxxxx bl c010c6e4 > > > ... > > > xxxxx: xxxxx bl c0791c8c > > > xxxxx: xxxxx movw r5, #23132 ; 0x5a5c > > > xxxxx: xxxxx vmrs r4, fpsid <- this is the fmrx instruction > > > > > > After the patching: > > > xxxxx: xxxxx bl c010c688 > > > xxxxx: xxxxx mov r0, r4 > > > xxxxx: xxxxx vmrs r5, fpsid <- this is the fmrx instruction > > > xxxxx: xxxxx bl c010c6e4 > > > > > > Signed-off-by: zhuqiuer > > > > This also fixes the issue I observed so > > > > Reviewed-by: Ard Biesheuvel > > Reviewed-by: Nathan Chancellor > > This can probably go in Russell's patch tracker? Yes. > Your patch had > > Cc: stable@vger.kernel.org > > in it, should this one as well? > Yes. > > > --- > > > arch/arm/vfp/vfpinstr.h | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h > > > index 3c7938fd40aa..ae2c9b9b7701 100644 > > > --- a/arch/arm/vfp/vfpinstr.h > > > +++ b/arch/arm/vfp/vfpinstr.h > > > @@ -68,14 +68,14 @@ > > > u32 __v; \ > > > asm(".fpu vfpv2\n" \ > > > "vmrs %0, " #_vfp_ \ > > > - : "=r" (__v) : : "cc"); \ > > > + : "=r" (__v) : : "memory", "cc"); \ > > > __v; \ > > > }) > > > > > > #define fmxr(_vfp_,_var_) \ > > > asm(".fpu vfpv2\n" \ > > > "vmsr " #_vfp_ ", %0" \ > > > - : : "r" (_var_) : "cc") > > > + : : "r" (_var_) : "memory", "cc") > > > > > > #else > > > > > > -- > > > 2.12.3 > > >