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Subject: Re: [RFC v3 08/16] clk: starfive: Add JH8100 North-West clock generator driver
From: Stephen Boyd <sboyd@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, jeeheng.sia@starfivetech.com, leyfoon.tan@starfivetech.com
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>, aou@eecs.berkeley.edu, conor@kernel.org, emil.renner.berthing@canonical.com, hal.feng@starfivetech.com, kernel@esmil.dk, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, p.zabel@pengutronix.de, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xingyu.wu@starfivetech.com
Date: Thu, 11 Apr 2024 00:49:25 -0700
User-Agent: alot/0.10

Quoting Sia Jee Heng (2024-01-10 05:31:20)
> diff --git a/drivers/clk/starfive/clk-starfive-jh8100-nw.c b/drivers/clk/=
starfive/clk-starfive-jh8100-nw.c
> new file mode 100644
> index 000000000000..018f5af6c777
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh8100-nw.c
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH8100 North-West Clock Driver
> + *
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
[...]
> +
> +static int jh8100_nwcrg_probe(struct platform_device *pdev)
> +{
> +       struct starfive_clk_priv *priv;
> +       unsigned int idx;
> +       int ret;
> +
> +       priv =3D devm_kzalloc(&pdev->dev,
> +                           struct_size(priv, reg, JH8100_NWCLK_NUM_CLKS),
> +                           GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       spin_lock_init(&priv->rmw_lock);
> +       priv->dev =3D &pdev->dev;
> +       priv->base =3D devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(priv->base))
> +               return PTR_ERR(priv->base);
> +
> +       for (idx =3D 0; idx < JH8100_NWCLK_NUM_CLKS; idx++) {
> +               u32 max =3D jh8100_nwcrg_clk_data[idx].max;
> +               struct clk_parent_data parents[4] =3D {};
> +               struct clk_init_data init =3D {
> +                       .name =3D jh8100_nwcrg_clk_data[idx].name,
> +                       .ops =3D starfive_clk_ops(max),
> +                       .parent_data =3D parents,
> +                       .num_parents =3D
> +                               ((max & STARFIVE_CLK_MUX_MASK) >> STARFIV=
E_CLK_MUX_SHIFT) + 1,
> +                       .flags =3D jh8100_nwcrg_clk_data[idx].flags,
> +               };
> +               struct starfive_clk *clk =3D &priv->reg[idx];
> +               unsigned int i;
> +
> +               for (i =3D 0; i < init.num_parents; i++) {
> +                       unsigned int pidx =3D jh8100_nwcrg_clk_data[idx].=
parents[i];
> +
> +                       if (pidx < JH8100_NWCLK_NUM_CLKS)
> +                               parents[i].hw =3D &priv->reg[pidx].hw;
> +                       else if (pidx =3D=3D JH8100_NWCLK_OSC)
> +                               parents[i].fw_name =3D "osc";

Please generate this one time with structures and use an index instead
of string names. This is faster in multiple ways, and the parent data is
copied anyway.

> +                       else if (pidx =3D=3D JH8100_NWCLK_APB_BUS)
> +                               parents[i].fw_name =3D "apb_bus";
> +                       else if (pidx =3D=3D JH8100_NWCLK_APB_BUS_PER4)
> +                               parents[i].fw_name =3D "apb_bus_per4";