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AJvYcCXntGoITGU7rr8MVxw8VuHf+C9Yhqh9WcuenkMbTTsfXO21ObLSGrCzeQN3hN7B+JN2eIx8kHrSRdTh84sS6rLzx84lXCgbVizaFHmg X-Gm-Message-State: AOJu0YyIWzS5+Z2OSpx6KTpdEm+vgS1/OKYie3MjZBWFqlbQbzWcZ/aK x+kO1ot5H1GnjpMplmsq/rnzcWA5XLcIPjui77d9cbNACprWj9gh5Zt3nHZ0yyuniRPU4YlGtqL c/A== X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:fc07:0:b0:5dc:4a5f:a5ee with SMTP id j7-20020a63fc07000000b005dc4a5fa5eemr19333pgi.1.1712863928433; Thu, 11 Apr 2024 12:32:08 -0700 (PDT) Date: Thu, 11 Apr 2024 12:32:06 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-2-xiong.y.zhang@linux.intel.com> <56a98cae-36c5-40f8-8554-77f9d9c9a1b0@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 01/41] perf: x86/intel: Support PERF_PMU_CAP_VPMU_PASSTHROUGH From: Sean Christopherson To: Jim Mattson Cc: Kan Liang , Xiong Zhang , pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 11, 2024, Sean Christopherson wrote: > On Thu, Apr 11, 2024, Jim Mattson wrote: > > On Thu, Apr 11, 2024 at 10:21=E2=80=AFAM Liang, Kan wrote: > > > On 2024-04-11 1:04 p.m., Sean Christopherson wrote: > > > > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > > >> From: Kan Liang > > > >> > > > >> Define and apply the PERF_PMU_CAP_VPMU_PASSTHROUGH flag for the ve= rsion 4 > > > >> and later PMUs > > > > > > > > Why? I get that is an RFC, but it's not at all obvious to me why t= his needs to > > > > take a dependency on v4+. > > > > > > The IA32_PERF_GLOBAL_STATUS_RESET/SET MSRs are introduced in v4. They > > > are used in the save/restore of PMU state. Please see PATCH 23/41. > > > So it's limited to v4+ for now. > >=20 > > Prior to version 4, semi-passthrough is possible, but IA32_PERF_GLOBAL_= STATUS > > has to be intercepted and emulated, since it is non-trivial to set bits= in > > this MSR. >=20 > Ah, then this _perf_ capability should be PERF_PMU_CAP_WRITABLE_GLOBAL_ST= ATUS or And now I see that the capabilities are arch agnostic, whereas GLOBAL_STATU= S obviously is not. Unless a writable GLOBAL_STATUS is a hard requirement fo= r perf to be able to support a mediated PMU, this capability probably doesn't need= to exist, e.g. KVM can check for a writable GLOBAL_STATUS just as easily as pe= rf (or perf can stuff x86_pmu_capability.writable_global_status directly).