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AJvYcCWKYr+XU7reD9kBMTESAcDuDq2HJSA03N6yCWgw2SVXYiG3/lvuVAfPSdUykcnagZdvdh50Ur6slts7AFLl2K93IIX0Y7CancGUHtm+ X-Gm-Message-State: AOJu0YxLkcMBaN4+n9RjGo9pivX33NKywQ8NAWNW+oFgl78k+b4XWUjU NEiTZnz4adlFv20j9CvfTzGIz7AOpASVgyR0zUXv0EW+JbKJ6SnviGB6Fu8JNjdLUqWbNaTdz7p lc+iiIAOv9QuK9mv3pNJNvg2R8u22MyCua7BD X-Received: by 2002:aa7:d889:0:b0:56e:5681:ff3e with SMTP id u9-20020aa7d889000000b0056e5681ff3emr59016edq.2.1712874644225; Thu, 11 Apr 2024 15:30:44 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-16-xiong.y.zhang@linux.intel.com> In-Reply-To: From: Jim Mattson Date: Thu, 11 Apr 2024 15:30:32 -0700 Message-ID: Subject: Re: [RFC PATCH 15/41] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL To: Sean Christopherson Cc: Xiong Zhang , pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 11, 2024 at 2:21=E2=80=AFPM Sean Christopherson wrote: > > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > + if (is_passthrough_pmu_enabled(&vmx->vcpu)) { > > + /* > > + * Setup auto restore guest PERF_GLOBAL_CTRL MSR at vm en= try. > > + */ > > + if (vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) > > + vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, 0); > > + else { > > + i =3D vmx_find_loadstore_msr_slot(&vmx->msr_autol= oad.guest, > > + MSR_CORE_PERF_GLOB= AL_CTRL); > > + if (i < 0) { > > + i =3D vmx->msr_autoload.guest.nr++; > > + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, > > + vmx->msr_autoload.guest.nr); > > + } > > + vmx->msr_autoload.guest.val[i].index =3D MSR_CORE= _PERF_GLOBAL_CTRL; > > + vmx->msr_autoload.guest.val[i].value =3D 0; > > Eww, no. Just make cpu_has_load_perf_global_ctrl() and VM_EXIT_SAVE_IA3= 2_PERF_GLOBAL_CTRL > hard requirements for enabling passthrough mode. And then have clear_ato= mic_switch_msr() > yell if KVM tries to disable loading MSR_CORE_PERF_GLOBAL_CTRL. Weren't you just complaining about the PMU version 4 constraint in another patch? And here, you are saying, "Don't support anything older than Sapphire Rapids." Sapphire Rapids has PMU version 4, so if we require VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, PMU version 4 is irrelevant.