Received-SPF: pass (google.com: domain of linux-kernel+bounces-141687-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Date: Thu, 11 Apr 2024 15:54:39 -0700
In-Reply-To: <CALMp9eTQr8ndf48uHHDem2ZkycdhAuVqz18+V1reEEfv0sx8qg@mail.gmail.com>
Precedence: bulk
Mime-Version: 1.0
References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com>
 <20240126085444.324918-29-xiong.y.zhang@linux.intel.com> <ZhhcAT7XiLHK3ZNQ@google.com>
 <CALMp9eTQr8ndf48uHHDem2ZkycdhAuVqz18+V1reEEfv0sx8qg@mail.gmail.com>
Message-ID: <ZhhqL2HKmcW9DAIY@google.com>
Subject: Re: [RFC PATCH 28/41] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at
 VM boundary
From: Sean Christopherson <seanjc@google.com>
To: Jim Mattson <jmattson@google.com>
Cc: Xiong Zhang <xiong.y.zhang@linux.intel.com>, pbonzini@redhat.com, 
	peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, 
	zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, 
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, 
	zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, 
	samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, 
	Xiong Zhang <xiong.y.zhang@intel.com>
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: quoted-printable

On Thu, Apr 11, 2024, Jim Mattson wrote:
> On Thu, Apr 11, 2024 at 2:54=E2=80=AFPM Sean Christopherson <seanjc@googl=
e.com> wrote:
> >
> > On Fri, Jan 26, 2024, Xiong Zhang wrote:
> > > +static void save_perf_global_ctrl_in_passthrough_pmu(struct vcpu_vmx=
 *vmx)
> > > +{
> > > +     struct kvm_pmu *pmu =3D vcpu_to_pmu(&vmx->vcpu);
> > > +     int i;
> > > +
> > > +     if (vm_exit_controls_get(vmx) & VM_EXIT_SAVE_IA32_PERF_GLOBAL_C=
TRL) {
> > > +             pmu->global_ctrl =3D vmcs_read64(GUEST_IA32_PERF_GLOBAL=
_CTRL);
> > > +     } else {
> > > +             i =3D vmx_find_loadstore_msr_slot(&vmx->msr_autostore.g=
uest,
> > > +                                             MSR_CORE_PERF_GLOBAL_CT=
RL);
> > > +             if (i < 0)
> > > +                     return;
> > > +             pmu->global_ctrl =3D vmx->msr_autostore.guest.val[i].va=
lue;
> >
> > As before, NAK to using the MSR load/store lists unless there's a *real=
ly* good
> > reason I'm missing.
>=20
> The VM-exit control, "save IA32_PERF_GLOBAL_CTL," first appears in
> Sapphire Rapids. I think that's a compelling reason.

Well that's annoying.  When was PMU v4 introduced?  E.g. if it came in ICX,=
 I'd
be sorely tempted to make VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL a hard require=
ment.

And has someone confirmed that the CPU saves into the MSR store list before
processing VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL?

Assuming we don't make VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL a hard requiremen=
t,
this code should be cleaned up and simplified.  It should be impossible to =
get
to this point with a passthrough PMU and no slot for saving guest GLOBAL_CT=
RL.

E.g. this could simply be:

	if (cpu_has_save_perf_global_ctrl())
		pmu->global_ctrl =3D vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL);
	else
		pmu->global_ctrl =3D *pmu->__global_ctrl;

where vmx_set_perf_global_ctrl() sets __global_ctrl to:

	pmu->__global_ctrl =3D &vmx->msr_autostore.guest.val[i].value;

KVM could store 'i', i.e. the slot, but in the end it's 4 bytes per vCPU (a=
ssuming
64-bit kernel, and an int to store the slot).

Oh, by the by, vmx_set_perf_global_ctrl() is buggy, as it neglects to *remo=
ve*
PERF_GLOBAL_CTRL from the lists if userspace sets CPUID multiple times.