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AJvYcCWgeSsqHHlZNgJCePTQ95guKy58txMmGfeCaGMYMeUpNvhEGfeTLT4w9KTtGP03j5lm3iu2IOf4iVgQRlOfZkY5VLaa+IBz/pXQvgCG X-Gm-Message-State: AOJu0YxfICMN6VgD7AJNb8TI3Lr3VBZnAKxjWNly97St0L0XCUNfrrBJ FiNIcTUQ8pqstH8/H9UJGO8kUAR0wiPWh8QT2Dk8orlEZ8Tf6Sy86vpS2eKD8FEfGQUgOdfnMGi BCg== X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:2c4e:b0:2a4:69fa:8b08 with SMTP id p14-20020a17090a2c4e00b002a469fa8b08mr2834pjm.4.1712878055952; Thu, 11 Apr 2024 16:27:35 -0700 (PDT) Date: Thu, 11 Apr 2024 16:27:34 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-16-xiong.y.zhang@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 15/41] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL From: Sean Christopherson To: Jim Mattson Cc: Xiong Zhang , pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 11, 2024, Jim Mattson wrote: > On Thu, Apr 11, 2024 at 2:21=E2=80=AFPM Sean Christopherson wrote: > > > > On Fri, Jan 26, 2024, Xiong Zhang wrote: > > > + if (is_passthrough_pmu_enabled(&vmx->vcpu)) { > > > + /* > > > + * Setup auto restore guest PERF_GLOBAL_CTRL MSR at vm = entry. > > > + */ > > > + if (vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) > > > + vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, 0); > > > + else { > > > + i =3D vmx_find_loadstore_msr_slot(&vmx->msr_aut= oload.guest, > > > + MSR_CORE_PERF_GL= OBAL_CTRL); > > > + if (i < 0) { > > > + i =3D vmx->msr_autoload.guest.nr++; > > > + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, > > > + vmx->msr_autoload.guest.nr= ); > > > + } > > > + vmx->msr_autoload.guest.val[i].index =3D MSR_CO= RE_PERF_GLOBAL_CTRL; > > > + vmx->msr_autoload.guest.val[i].value =3D 0; > > > > Eww, no. Just make cpu_has_load_perf_global_ctrl() and VM_EXIT_SAVE_I= A32_PERF_GLOBAL_CTRL > > hard requirements for enabling passthrough mode. And then have clear_a= tomic_switch_msr() > > yell if KVM tries to disable loading MSR_CORE_PERF_GLOBAL_CTRL. >=20 > Weren't you just complaining about the PMU version 4 constraint in > another patch? And here, you are saying, "Don't support anything older > than Sapphire Rapids." Heh, I didn't realize VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL was SPR+ when I wr= ote this, I thought it existed alongside the "load" controls. > Sapphire Rapids has PMU version 4, so if we require > VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, PMU version 4 is irrelevant.