Received-SPF: pass (google.com: domain of linux-kernel+bounces-142006-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Message-ID: <58956ebc474b993e6da1d6689ecb9324.sboyd@kernel.org>
Content-Type: text/plain; charset="utf-8"
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <MA0P287MB2822BC109267BD20922FB581FE052@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
References: <cover.1711692169.git.unicorn_wang@outlook.com> <816122e9f22ddd9927e81e627be7f4683ba5c9e8.1711692169.git.unicorn_wang@outlook.com> <433e01f22ce5472aeb28cf0182d951bd.sboyd@kernel.org> <MA0P287MB2822BC109267BD20922FB581FE052@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
Subject: Re: [PATCH v13 4/5] clk: sophgo: Add SG2042 clock driver
From: Stephen Boyd <sboyd@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>, Chen Wang <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, haijiao.liu@sophgo.com, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, samuel.holland@sifive.com, xiaoguang.xing@sophgo.com
Date: Thu, 11 Apr 2024 22:55:05 -0700
User-Agent: alot/0.10

Quoting Chen Wang (2024-04-11 05:58:05)
>=20
> On 2024/4/11 12:11, Stephen Boyd wrote:
> > Quoting Chen Wang (2024-03-28 23:21:40)
> >> +static const u32 sg2042_mux_table[] =3D {1, 0};
> >> +
> >> +static const char *const clk_mux_ddr01_p[] =3D {
> >> +                       "clk_div_ddr01_0", "clk_div_ddr01_1"};
> >> +static const char *const clk_mux_ddr23_p[] =3D {
> >> +                       "clk_div_ddr23_0", "clk_div_ddr23_1"};
> >> +static const char *const clk_mux_rp_cpu_normal_p[] =3D {
> >> +                       "clk_div_rp_cpu_normal_0", "clk_div_rp_cpu_nor=
mal_1"};
> >> +static const char *const clk_mux_axi_ddr_p[] =3D {
> >> +                       "clk_div_axi_ddr_0", "clk_div_axi_ddr_1"};
> >> +
> >> +static struct sg2042_mux_clock sg2042_mux_clks[] =3D {
> >> +       SG2042_MUX(MUX_CLK_DDR01, "clk_mux_ddr01", clk_mux_ddr01_p,
> > Please use struct clk_parent_data or struct clk_hw directly instead of
> > string names.
>=20
> Hi, Stephen,
>=20
> I understand that for clk_init_data, parent_names/parent_data/parent_hws =

> are all acceptable. Why do you only suggest me to use=20
> parent_data/parent_hws here? Can you please explain?

Using parent_names requires a global string search for that clk. Using
clk_parent_data or parent_hws reduces that search significantly,
speeding things up. Not using any strings furthermore speeds it up, i.e.
using an index when the clk is external to the device and a clk_hw
pointer when the clk is internal to the device. We speed things up by
removing string comparisons, of which there are many. Any new code
should be using direct pointers or an index, no strings.