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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 16bbae4e-e6a0-4066-ce2d-08dc5ad13a43 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2024 09:16:25.1656 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: S6Q56gAEE/jt1Qy5DDso3fymuSC/Qt/xA2bBTK+J4w49cFi19yYEmFQARjxaK8KCeug9VGGhBCa9f7hyT28kYw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4664 X-OriginatorOrg: intel.com > From: Jacob Pan > Sent: Saturday, April 6, 2024 6:31 AM >=20 > +#ifdef CONFIG_X86_POSTED_MSI > + > +/* Posted Interrupt Descriptors for coalesced MSIs to be posted */ > +DEFINE_PER_CPU_ALIGNED(struct pi_desc, posted_interrupt_desc); 'posted_msi_desc' to be more accurate?