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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DS0PR11MB7529.namprd11.prod.outlook.com (2603:10b6:8:141::20) by DS0PR11MB6398.namprd11.prod.outlook.com (2603:10b6:8:c9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.21; Fri, 12 Apr 2024 09:31:09 +0000 Received: from DS0PR11MB7529.namprd11.prod.outlook.com ([fe80::d244:15cd:1060:941a]) by DS0PR11MB7529.namprd11.prod.outlook.com ([fe80::d244:15cd:1060:941a%6]) with mapi id 15.20.7430.045; Fri, 12 Apr 2024 09:31:09 +0000 Message-ID: <5e17af59-e544-4c5e-a718-2cd77b8a07a4@intel.com> Date: Fri, 12 Apr 2024 17:34:42 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] iommu/vt-d: Remove caching mode check before device TLB flush Content-Language: en-US To: Baolu Lu , CC: Kevin Tian , Jacob Pan , Joerg Roedel , Will Deacon , Robin Murphy , References: <20240410055823.264501-1-baolu.lu@linux.intel.com> <7e78917f-f84c-4e98-a612-73b8013ae367@intel.com> <0231631b-44ca-45ee-adf9-0a5c8852cc27@linux.intel.com> <776ef2f1-747d-46f0-94be-747c6fca8ce0@linux.intel.com> From: Yi Liu In-Reply-To: <776ef2f1-747d-46f0-94be-747c6fca8ce0@linux.intel.com> Content-Type: text/plain; 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The caching mode is >>>>> irrelevant to the device TLB , therefore there is no need to check >>>>> it before a device TLB invalidation operation. >>>>> >>>>> iommu_flush_iotlb_psi() is called in map and unmap paths. The caching >>>>> mode check before device TLB invalidation will cause device TLB >>>>> invalidation always issued if IOMMU is not running in caching mode. >>>>> This is wrong and causes unnecessary performance overhead. >>>> >>>> I don't think the original code is wrong. As I replied before, if CM==0, >>>> the iommu_flush_iotlb_psi() is only called in unmap path, in which the >>>> @map is false. [1] The reason to make the change is to make the logic >>>> simpler. ???? >>> >>> Oh, I see. There is a magic >>> >>>          if (cap_caching_mode(iommu->cap) && !domain->use_first_level) >>>                  iommu_flush_iotlb_psi(iommu, domain, pfn, pages, 0, 1); >>> >>> in __mapping_notify_one(). >>> >>> So if it's caching mode, then >>> >>>   - iommu_flush_iotlb_psi() will be called with @map=1 from >>>     __mapping_notify_one(), "!cap_caching_mode(iommu->cap) || !map" is >>>     not true, and device TLB is not invalidated. >>>   - iommu_flush_iotlb_psi() will also be called with @map=0 from >>>     intel_iommu_tlb_sync(), device TLB is issued there. >>> >>> That's the expected behavior for caching mode. >>> >>> If it's not the caching mode, then >>> >>>   - iommu_flush_iotlb_psi() will be called with @map=0 from >>>     intel_iommu_tlb_sync(), device TLB is issued there. >>> >>> That's also the expected behavior. >>> >>> So the existing code is correct but obscure and difficult to understand, >>> right? If so, we should make this patch as a cleanup rather than a fix. >> >> aha, yes. As the below table, iommu_flush_iotlb_psi() does flush device TLB >> as expected. But there is a NA case. When CM==0, it should not be possible >> to call iommu_flush_iotlb_psi() with @map==1 as cache invalidation is not >> required when CM==0. So the existing code logic is really confusing, >> checking @map is enough and clearer. Since the old code works, so perhaps >> no fix tag is needed. :) >> >> +----+------+-----------+------------+ >> |  \       |            |            | >> |   \ @map |            |            | >> | CM \     |      0     |     1      | >> |     \    |            |            | >> +------+---+------------+------------+ >> |          |            |            | >> |     0    |      Y     |     NA     | >> +----------+------------+------------+ >> |          |            |            | >> |     1    |      Y     |     N      | >> +----------+------------+------------+ >> >> Y means flush dev-TLB please >> N means no need to flush dev-TLB >> NA means not applied > > Yes. We have the same understanding now. :-) yeah, would be helpful to refine the commit message w.r.t. this change. >> >> BTW. I think it is better to have the below change in a separate patch. >> The below change does fix a improper dev-TLB flushing behavior. Also >> how about Kevin's concern in the end of [1]. I didn't see your respond >> about it. > > I had an offline discussion with him and I included the conclusion in > the commit message of this patch. ok. So the key reason is that intel_flush_iotlb_all() is not called at all if CM==1 after that commit. So there is nothing fixed by this change. right? This just makes the logic cleaner. Perhaps no need for a fix tag. Reviewed-by: Yi Liu -- Regards, Yi Liu