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Date: Fri, 12 Apr 2024 12:37:08 +0100
From: Conor Dooley <conor.dooley@microchip.com>
To: Charlie Jenkins <charlie@rivosinc.com>
CC: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley
	<paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou
	<aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Conor Dooley
	<conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec
	<jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Evan Green
	<evan@rivosinc.com>, =?iso-8859-1?Q?Cl=E9ment_L=E9ger?=
	<cleger@rivosinc.com>, Jonathan Corbet <corbet@lwn.net>, Shuah Khan
	<shuah@kernel.org>, <linux-riscv@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Palmer Dabbelt
	<palmer@rivosinc.com>, <linux-arm-kernel@lists.infradead.org>,
	<linux-sunxi@lists.linux.dev>, <linux-doc@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>
Subject: Re: [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector
 enabled
Message-ID: <20240412-thrill-amnesty-019897f21466@wendy>
References: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com>
 <20240411-dev-charlie-support_thead_vector_6_9-v1-15-4af9815ec746@rivosinc.com>
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On Thu, Apr 11, 2024 at 09:11:21PM -0700, Charlie Jenkins wrote:
> xtheadvector is not vector 1.0 compatible, but it can leverage all of
> the same save/restore routines as vector plus
> riscv_v_first_use_handler(). vector 1.0 and xtheadvector are mutually
> exclusive so there is no risk of overlap.

I think this not okay to do - if a program checks hwcap to see if vector
is supported they'll get told it is on T-Head system where only the 0.7.1
is.

>=20
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>=20
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur=
e.c
> index 41a4d2028428..59f628b1341c 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -647,9 +647,13 @@ static void __init riscv_fill_hwcap_from_isa_string(=
unsigned long *isa2hwcap)
>  		 * Many vendors with T-Head CPU cores which implement the 0.7.1
>  		 * version of the vector specification put "v" into their DTs.
>  		 * CPU cores with the ratified spec will contain non-zero
> -		 * marchid.
> +		 * marchid. Only allow "v" to be set if xtheadvector is present.
>  		 */
> -		if (acpi_disabled && this_vendorid =3D=3D THEAD_VENDOR_ID &&
> +		if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,
> +							   RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {
> +			this_hwcap |=3D isa2hwcap[RISCV_ISA_EXT_v];
> +			set_bit(RISCV_ISA_EXT_v, isainfo->isa);
> +		} else if (acpi_disabled && this_vendorid =3D=3D THEAD_VENDOR_ID &&
>  		    this_archid =3D=3D 0x0) {
>  			this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_v];
>  			clear_bit(RISCV_ISA_EXT_v, isainfo->isa);
> @@ -776,6 +780,15 @@ static int __init riscv_fill_hwcap_from_ext_list(uns=
igned long *isa2hwcap)
> =20
>  		of_node_put(cpu_node);
> =20
> +		/*
> +		 * Enable kernel vector routines if xtheadvector is present
> +		 */
> +		if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,
> +							   RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {
> +			this_hwcap |=3D isa2hwcap[RISCV_ISA_EXT_v];
> +			set_bit(RISCV_ISA_EXT_v, isainfo->isa);
> +		}
> +
>  		/*
>  		 * All "okay" harts should have same isa. Set HWCAP based on
>  		 * common capabilities of every "okay" hart, in case they don't.
>=20
> --=20
> 2.44.0
>=20

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