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Fri, 12 Apr 2024 04:40:10 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Fri, 12 Apr 2024 04:40:06 -0700 Date: Fri, 12 Apr 2024 12:39:15 +0100 From: Conor Dooley To: Charlie Jenkins CC: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , , , , Palmer Dabbelt , , , , Subject: Re: [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Message-ID: <20240412-candle-duffel-a612bab6e2a7@wendy> References: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com> <20240411-dev-charlie-support_thead_vector_6_9-v1-16-4af9815ec746@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="mRHPCw/Vg3OkuwNh" Content-Disposition: inline In-Reply-To: <20240411-dev-charlie-support_thead_vector_6_9-v1-16-4af9815ec746@rivosinc.com> --mRHPCw/Vg3OkuwNh Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Apr 11, 2024 at 09:11:22PM -0700, Charlie Jenkins wrote: > +static void hwprobe_isa_vendor_ext0(struct riscv_hwprobe *pair, > + const struct cpumask *cpus) > +{ > + int cpu; > + u64 missing = 0; > + > + pair->value = 0; > + > + struct riscv_hwprobe mvendorid = { > + .key = RISCV_HWPROBE_KEY_MVENDORID, > + .value = 0 > + }; > + > + hwprobe_arch_id(&mvendorid, cpus); > + > + /* Set value to zero if CPUs in the set do not have the same vendor. */ > + if (mvendorid.value == -1ULL) > + return; > + > + /* > + * Loop through and record vendor extensions that 1) anyone has, and > + * 2) anyone doesn't have. > + */ > + for_each_cpu(cpu, cpus) { > + struct riscv_isainfo *isavendorinfo = &hart_isa_vendor[cpu]; > + > +#define VENDOR_EXT_KEY(ext) \ > + do { \ > + if (__riscv_isa_vendor_extension_available(isavendorinfo->isa, \ > + RISCV_ISA_VENDOR_EXT_##ext)) \ > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + else \ > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > + } while (false) > + > + /* > + * Only use VENDOR_EXT_KEY() for extensions which can be exposed to userspace, > + * regardless of the kernel's configuration, as no other checks, besides > + * presence in the hart_vendor_isa bitmap, are made. > + */ > + VENDOR_EXT_KEY(XTHEADVECTOR); Reading the comment here, I don't think you can do this. All vector support in userspace is continent on kernel configuration options. > + > +#undef VENDOR_EXT_KEY > + } > + > + /* Now turn off reporting features if any CPU is missing it. */ > + pair->value &= ~missing; > +} --mRHPCw/Vg3OkuwNh Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZhkdYwAKCRB4tDGHoIJi 0oeDAP4tnQJ0meOXf8oUmHOUiJb0NFMEHSi8MWLLKw5qh80wlwD/R11jlcsqR/Uh O70O3h3uu21ywXzH0Akw/ETQIVC34As= =Jjh4 -----END PGP SIGNATURE----- --mRHPCw/Vg3OkuwNh--