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Date: Fri, 12 Apr 2024 14:32:35 +0100
From: Will Deacon <will@kernel.org>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>,
	Arnd Bergmann <arnd@arndb.de>, Huacai Chen <chenhuacai@kernel.org>,
	Waiman Long <longman@redhat.com>, Boqun Feng <boqun.feng@gmail.com>,
	Guo Ren <guoren@kernel.org>, Rui Wang <wangrui@loongson.cn>,
	WANG Xuerui <kernel@xen0n.name>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>, linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org, torvalds@linux-foundation.org,
	mpe@ellerman.id.au
Subject: Re: [PATCH 2/2] mmiowb: Hook up mmiowb helpers to mutexes as well as
 spinlocks
Message-ID: <20240412133235.GA27868@willie-the-truck>
References: <20240301130532.3953167-1-chenhuacai@loongson.cn>
 <20240301130532.3953167-2-chenhuacai@loongson.cn>
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On Fri, Mar 01, 2024 at 09:05:32PM +0800, Huacai Chen wrote:
> Commit fb24ea52f78e0d595852e ("drivers: Remove explicit invocations of
> mmiowb()") remove all mmiowb() in drivers, but it says:
> 
> "NOTE: mmiowb() has only ever guaranteed ordering in conjunction with
> spin_unlock(). However, pairing each mmiowb() removal in this patch with
> the corresponding call to spin_unlock() is not at all trivial, so there
> is a small chance that this change may regress any drivers incorrectly
> relying on mmiowb() to order MMIO writes between CPUs using lock-free
> synchronisation."
> 
> The mmio in radeon_ring_commit() is protected by a mutex rather than a
> spinlock, but in the mutex fastpath it behaves similar to spinlock. We
> can add mmiowb() calls in the radeon driver but the maintainer says he
> doesn't like such a workaround, and radeon is not the only example of
> mutex protected mmio.

Oh no! Ostrich programming is real!

https://lore.kernel.org/lkml/CAHk-=wgbnn7x+i72NqnvXotbxjsk2Ag56Q5YP0OSvhY9sUk7QA@mail.gmail.com/

> So we extend the mmiowb tracking system from spinlock to mutex, hook up
> mmiowb helpers to mutexes as well as spinlocks.
> 
> Without this, we get such an error when run 'glxgears' on weak ordering
> architectures such as LoongArch:
> 
> radeon 0000:04:00.0: ring 0 stalled for more than 10324msec
> radeon 0000:04:00.0: ring 3 stalled for more than 10240msec
> radeon 0000:04:00.0: GPU lockup (current fence id 0x000000000001f412 last fence id 0x000000000001f414 on ring 3)
> radeon 0000:04:00.0: GPU lockup (current fence id 0x000000000000f940 last fence id 0x000000000000f941 on ring 0)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> radeon 0000:04:00.0: scheduling IB failed (-35).
> [drm:radeon_gem_va_ioctl [radeon]] *ERROR* Couldn't update BO_VA (-35)
> 
> Link: https://lore.kernel.org/dri-devel/29df7e26-d7a8-4f67-b988-44353c4270ac@amd.com/T/#t

Hmm. It's hard to tell from that thread whether you're really falling
afoul of the problems that mmiowb() tries to solve or whether Loongson
simply doesn't have enough ordering in its MMIO accessors.

The code you proposed has:

	mmiowb(); /* Make sure wptr is up-to-date for hw */

but mmiowb() is really about ensuring order with MMIO accesses from a
different CPU that subsequently takes the lock.

So please can you explain a bit more about the failing case? I'm worried
that mmiowb() may be the wrong tool for the job here.

Thanks,

Will