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From: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
To: "linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>
CC: Stephan Gerhold <stephan@gerhold.net>,
        Volodymyr Babchuk
	<Volodymyr_Babchuk@epam.com>,
        "stable@vger.kernel.org"
	<stable@vger.kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad
 Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley
	<conor+dt@kernel.org>,
        Bhupesh Sharma <bhupesh.sharma@linaro.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 1/2] arm64: dts: qcom: sa8155p-adp: fix SDHC2 CD pin
 configuration
Thread-Topic: [PATCH v3 1/2] arm64: dts: qcom: sa8155p-adp: fix SDHC2 CD pin
 configuration
Thread-Index: AQHajQwYOQ9To8w33EaflpLdE0ZqmQ==
Date: Fri, 12 Apr 2024 19:03:25 +0000
Message-ID: <20240412190310.1647893-1-volodymyr_babchuk@epam.com>
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There are two issues with SDHC2 configuration for SA8155P-ADP,
which prevent use of SDHC2 and causes issues with ethernet:

- Card Detect pin for SHDC2 on SA8155P-ADP is connected to gpio4 of
  PMM8155AU_1, not to SoC itself. SoC's gpio4 is used for DWMAC
  TX. If sdhc driver probes after dwmac driver, it reconfigures
  gpio4 and this breaks Ethernet MAC.

- pinctrl configuration mentions gpio96 as CD pin. It seems it was
  copied from some SM8150 example, because as mentioned above,
  correct CD pin is gpio4 on PMM8155AU_1.

This patch fixes both mentioned issues by providing correct pin handle
and pinctrl configuration.

Fixes: 0deb2624e2d0 ("arm64: dts: qcom: sa8155p-adp: Add support for uSD ca=
rd")
Cc: stable@vger.kernel.org
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

In v3:
 - Moved regulator changes to a separate patch
 - Renamed pinctrl node
 - Moved pinctrl node so it will appear in alphabetical order
In v2:
 - Added "Fixes:" tag
 - CCed stable ML
 - Fixed pinctrl configuration
 - Extended voltage range for L13C voltage regulator
---
 arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 30 ++++++++++--------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts=
/qcom/sa8155p-adp.dts
index 5e4287f8c8cd1..b2cf2c988336c 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -367,6 +367,16 @@ queue0 {
 	};
 };
=20
+&pmm8155au_1_gpios {
+	pmm8155au_1_sdc2_cd: sdc2-cd-default-state {
+		pins =3D "gpio4";
+		function =3D "normal";
+		input-enable;
+		bias-pull-up;
+		power-source =3D <0>;
+	};
+};
+
 &qupv3_id_1 {
 	status =3D "okay";
 };
@@ -384,10 +394,10 @@ &remoteproc_cdsp {
 &sdhc_2 {
 	status =3D "okay";
=20
-	cd-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>;
+	cd-gpios =3D <&pmm8155au_1_gpios 4 GPIO_ACTIVE_LOW>;
 	pinctrl-names =3D "default", "sleep";
-	pinctrl-0 =3D <&sdc2_on>;
-	pinctrl-1 =3D <&sdc2_off>;
+	pinctrl-0 =3D <&sdc2_on &pmm8155au_1_sdc2_cd>;
+	pinctrl-1 =3D <&sdc2_off &pmm8155au_1_sdc2_cd>;
 	vqmmc-supply =3D <&vreg_l13c_2p96>; /* IO line power */
 	vmmc-supply =3D <&vreg_l17a_2p96>;  /* Card power line */
 	bus-width =3D <4>;
@@ -505,13 +515,6 @@ data-pins {
 			bias-pull-up;		/* pull up */
 			drive-strength =3D <16>;	/* 16 MA */
 		};
-
-		sd-cd-pins {
-			pins =3D "gpio96";
-			function =3D "gpio";
-			bias-pull-up;		/* pull up */
-			drive-strength =3D <2>;	/* 2 MA */
-		};
 	};
=20
 	sdc2_off: sdc2-off-state {
@@ -532,13 +535,6 @@ data-pins {
 			bias-pull-up;		/* pull up */
 			drive-strength =3D <2>;	/* 2 MA */
 		};
-
-		sd-cd-pins {
-			pins =3D "gpio96";
-			function =3D "gpio";
-			bias-pull-up;		/* pull up */
-			drive-strength =3D <2>;	/* 2 MA */
-		};
 	};
=20
 	usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
--=20
2.44.0