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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0a718cd3-d0ff-48ab-8d16-d513d95563d3@citrix.com> On Fri, Apr 12, 2024 at 11:36:04AM +0100, Andrew Cooper wrote: > On 12/04/2024 6:20 am, Josh Poimboeuf wrote: > > On Thu, Apr 11, 2024 at 09:17:27PM -0700, Josh Poimboeuf wrote: > >> On Thu, Apr 11, 2024 at 08:57:42PM -0700, Josh Poimboeuf wrote: > >>> For similar reasons I'm thinking we should also remove the non-eIBRS > >>> version (SPECTRE_V2_LFENCE). > >> Actually I guess that's still the default mitigation for AMD so I'll > >> leave that one in. > > Never mind, I forgot that got deprecated for AMD. > > And then became necessary on two Atoms, although I can't for the life of > of me find Intel's footnote about this in the maze of speculation docs... Found it on this page [1] but it doesn't seem to be a very confident endorsement. And Linux doesn't seem to enable it for those parts regardless. IntelĀ® Atom Goldmont Plus and Tremont Mitigation Retpoline may not be a fully effective branch target injection mitigation on processors which are based on Intel Atom microarchitectures code named Goldmont Plus and Tremont, as documented in our existing guidance. On such processors, an LFENCE;JMP sequence may be an alternative for retpoline, although this is not architecturally guaranteed. Instructions may still be speculatively executed at the predicted near JMP target, which can allow some forms of shallow gadgets (for example, revealing register values) to be transiently executed. Intel is not currently evaluating LFENCE;JMP as an option other than for processors based on Goldmont Plus and Tremont microarchitectures, given the possibility of a sufficiently large transient window to execute a disclosure gadget. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html -- Josh